Scheduling computation and communication on a software-defined photonic Network-on-Chip architecture for high-performance real-time systems

Temuçin, Hüseyin; İmre, Kayhan M.

doi:10.1016/j.sysarc.2018.07.007

Cited by 9 publications

(4 citation statements)

References 27 publications

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“…In 2018, Temuçin and Imre presented a Software-Defined Photonic Network-on-Chip [ 49 ]. They aimed to centralize a contention-free and conflict-free scheduling algorithm to solve the routing and wavelength assignment in optical networks.…”

Section: Literature Reviewmentioning

confidence: 99%

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

et al. 2021

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Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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Section: Literature Reviewmentioning

confidence: 99%

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

et al. 2021

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“…This plane consists of the two bottom layers, the Optical (switching) layer with Fan in/out process and the Control layer. Based on the architecture described in [31], A 16×16 mesh is constructed from 4×4 photonic switches connected to form a mesh topology with 4×4 clusters, The clusters are generally small in sizes, such as 2×2, 3×3, 4×4, or 5×5, that what makes up the data plane of the software-defined network. In our architecture, we used a 4x4 non-blocking Straight-Path switch from switch designs described in Fig.…”

Section: ) Processing Planementioning

confidence: 99%

“…In [31], The control plane is distributed to the processing nodes; each node controls and configures a photonic switch using a dominating node in each row in each cluster. Core concentration is accomplished by using ordinary networkside concentration, shown in Fig.…”

Section: ) Processing Planementioning

confidence: 99%

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

et al. 2021

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Photonic networks and software-defined networks are two promising technologies to improve network-onchips performance, scalability, and resource utilization. Several architectures suffer from scaling limitations, high-power consumption, and noise interference drawbacks. In this paper, an enhanced photonic network-on-chip architecture called (SD-PNoC) is presented. The proposed architecture based on a hybrid hardware-software approach, and a Software-Defined Management Orchestrator (SDMO) to separate the network control and data forwarding planes. This orchestrator has hosted on the upper hardware router as a virtual layer capable of dynamic management. It reconfigures data forwarding paths and allows dynamic execution of different algorithms in real-time, as it scales the proposed topology based on both applications and the network requirements. The proposed SD-PNoC architecture, hierarchical communication protocols, and orchestrator management policies were implemented, simulated, and tested using a customized Phoenix-SIM framework in the OMNIT++ simulation environment. Numerous simulation experiments under different conditions have been performed and have proven that the performance of the proposed architecture is better than that of the conventional electronic network on chip (ENoC). Furthermore, simulation results without using the management policies showed that the latency is reduced by 46% and 25.5% for the 4x4 and 8x8 network structures, respectively. While the power consumption is reduced by 76.5% and 78.5% for the 4x4 and 8x8 network structures, respectively. Besides, the chip area is reduced by 33.4%. Moreover, simulation results of SDMO with using the management policies for the 8x8 network structures increased the enhancement of latency from 25.5% to 37.3% and the power consumption from 78.5% to approximately 80%, which assure the ability of the proposed architecture to remarkably enhance the overall performance of complex network-on-chip structures.

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“…However, such structures have some obvious disadvantages, including complicated design process, high power consumption, unpredictable delays and non-scalability. Therefore, the Networkon-Chip(NoC), which integrates a large number of processing elements(PEs), memory elements and a communication network connecting them, has been developed to replace traditional bus structures to improve the communication efficiency among different cores [1] and the overall system performance [2]. This new trend brings about a set of challenges, one of which is cache distribution among cores.…”

Section: Introductionmentioning

confidence: 99%

Partially shared cache and adaptive replacement algorithm for NoC-based many-core systems

Yang

Wang

et al. 2019

Journal of Systems Architecture

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The Network-on-Chip(NoC) is a promising alternative to traditional bus-based architectures that has been widely applied to interconnect multi/many-core systems due to its scalable and modular design. Undoubtedly, the memory wall problem is one of the most important challenges; however, this problem can now be somewhat be alleviated by cache subsystems. In this paper, to overcome the high resource consumption and low data-sharing rate problems of the private cache scheme, we propose a partially shared cache structure and a corresponding replacement algorithm based on a mesh NoC. In this scheme, the L2 cache is shared by each group of four cores that connected as a cluster to a given node by the local bus. To maximize the performance of this partially shared cache structure, we propose a core-aware re-reference interval prediction (CA-RRIP) replacement algorithm. The algorithm performs dynamic virtual partitioning on the partially shared cache; the core that initiated the cache access request will be given top priority when a cache area needs to be replaced or inserted. This approach guarantees cache exclusivity and can mitigate interactions among cores using different access patterns. We implement the traditional private, the proposed partially shared and the row-shared cache subsystems in our experiments. The comparisons indicate that the overall system resource occupation can be reduced by 20% with the same number of cores, and the instructions per cycle(IPC) of the system could increase by up to 49.2%. Moreover, the system throughput(STP) increased by an average of 5.89%. Our experimental results showed that the proposed CA-RRIP algorithm also reduces the average cache miss rate of the system under various cache access patterns.

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Scheduling computation and communication on a software-defined photonic Network-on-Chip architecture for high-performance real-time systems

Cited by 9 publications

References 27 publications

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

Partially shared cache and adaptive replacement algorithm for NoC-based many-core systems

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