The complexity of System-On-Chip(SOC) design is increasing continuously due to the multidimensional optimization requirements, while integrating complex intellectual property (IP) blocks. The interconnectivity topologies between IPs are playing a vital role in deciding the performance of the SOCs. This paper investigates the existing code division multiple access (CDMA) based network on chip (NOC) architectures. The work presented here explains a variant of CDMA based NOC scheme, which is best suitable at the base band level implementation for dynamic bandwidth management. A six node globallyasynchronous locally-synchronous (GALS) type NOC is realized at RTL level, with two different controller architectures. Both vary in terms of key management and control mechanism. The scheduler-built-in-ring type architecture, with its ease in placement and routing is suitable for complex SOCs. The architectures are implemented in VHDL and verified at simulation level. The Xilinx FPGA synthesis results promise more than 200 MHz clock speeds resulting in 1.6 Gbps data throughput over 32 bit ring bus on Virtex-6 LX series FPGAs.The complexity of System-On-Chip (SOC) design is increasing continuously due to the multidimensional optimization requirements, while integrating complex intellectual property (IP) blocks. The continuously evolving multimedia algorithms and wireless protocols are demanding silicon level revisions of SOCs during their lifecycle. The present day IP based design paradigm is influencing the total silicon chain. The industry wise thrust to achieve uniformity in IP interfaces and interconnectivity is the fact demonstrating the importance of interface issues among IP blocks.Even though several bus architectures are evolved to address the interconnectivity aspects, majority of them are only variants of conventional master-slave bus systems. The present day architectures suffer from following disadvantages.• Not designed to exploit high speed serial bus standards, which are available today. • To handle simple to complex IPs, a common interface specification is not possible. • VLSI routing aspects and related issues are not considered by several bus specifications.• Conventional address and data bus topologies leads lot of wiring in chips. • Dynamic configuration of bus bandwidths based on run time IP demands is not considered. • Most of the bus specifications are designed for convenience at the protocol layer, not visualizing the overheads at physical layer level.To overcome such challenges CDMA based approaches [1] are being proposed. The historical improvisation from monolithic [2] bus-based interconnect architectures to hierarchical system integration using multiple smaller buses connected through repeaters or bridges does not yield a general and scalable solution. The global timing improvisation [2] needs complete redesign of the SOC interconnect architectures.In this paradigm the research on NOC architectures with completely new design approaches assumes great importance. The concept of using CDMA as a multi...