Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit

Šůcha, Přemysl; Pohl, Z.; Hanzálek, Zdeněk

doi:10.1109/rttas.2004.1317287

Cited by 12 publications

(4 citation statements)

References 16 publications

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“…Although the RLS algorithm may converge more quickly than GSFAP, it is at the cost of a greatly reduced sampling rate. Sucha et al [2004] present an implementation of a 129-tap QR-RLS-based adaptive filter capable of operating on signals sampled at rate of 44kHz. This is a significant achievement on a resource-constrained Xilinx XC2V1000-4 device.…”

Section: Related Workmentioning

confidence: 99%

GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems

Tichý

Schier

Gregg

2010

ACM Trans. Embed. Comput. Syst.

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Adaptive filters are widely used in many applications of digital signal processing. Digital communications and digital video broadcasting are just two examples. Traditionally, small embedded systems have employed the least computationally intensive filter adaptive algorithms, such as normalized least mean squares (NLMS). This article shows that FPGA devices are a highly suitable platform for more computationally intensive adaptive algorithms. We present an optimized core which implements GSFAP. GSFAP is an algorithm with far superior adaptation properties than NLMS, and with only slightly higher computational complexity. To further optimize resource requirements we use logarithmic arithmetic, rather than conventional floating point, within the custom core. Our design makes effective use of the pipelined logarithmic addition units, and takes advantage of the very low cost of logarithmic multiplication and division. The resulting GSFAP core can be clocked at more than 80MHz on a one million-gate Xilinx XC2V1000-4 device. The core can be used to implement adaptive filters of orders 20 to 1000 performing echo cancellation on speech signals at a sampling rate exceeding 50kHz. For comparison, we implemented a similar NLMS core and found that although it is slightly smaller than the GSFAP core and allows a higher signal sampling rate for the corresponding filter orders, the GSFAP core has adaptation properties that are much superior to NLMS, and that our core can provide very sophisticated adaptive filtering capabilities for resource-constrained embedded systems.

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Section: Related Workmentioning

confidence: 99%

GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems

Tichý

Schier

Gregg

2010

ACM Trans. Embed. Comput. Syst.

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“…In order to exploit the maximal possible parallelism in the implementation of the RLS lattice filter, the cyclic scheduling of the RLS lattice inner loop was used [20,31]. It was found that the addition hardware macro is utilized by less than 25%.…”

Section: Alu and Schedulingmentioning

confidence: 99%

Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA

Pohl

Tichý

Kadlec

2008

EURASIP J. Adv. Signal Process.

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A high performance RLS lattice filter with the estimation of an unknown order and forgetting factor of identified system was developed and implemented as a PCORE coprocessor for Xilinx EDK. The coprocessor implemented in FPGA hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programming and debugging of hardware accelerated DSP applications. The RLS lattice core extended by the order and forgetting factor estimation was implemented using the logarithmic numbers system (LNS) arithmetic. An optimal mapping of the RLS lattice onto the LNS arithmetic units found by the cyclic scheduling was used. The schedule allows us to run four independent filters in parallel on one arithmetic macro set. The coprocessor containing the RLS lattice core is highly configurable. It allows to exploit the modular structure of the RLS lattice filter and construct the pipelined serial connection of filters for even higher performance. It also allows to run independent parallel filters on the same input with different forgetting factors in order to estimate which order and exponential forgetting factor better describe the observed data. The FPGA coprocessor implementation presented in the paper is able to evaluate the RLS lattice filter of order 504 at 12 kHz input data sampling rate. For the filter of order up to 20, the probability of order and forgetting factor hypotheses can be continually estimated. It has been demonstrated that the implemented coprocessor accelerates the Microblaze solution up to 20 times. It has also been shown that the coprocessor performs up to 2.5 times faster than highly optimized solution using 50 MIPS SHARC DSP processor, while the Microblaze is capable of performing another tasks concurrently.

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“…in robotics industry ( [1]; [2]), in manufacturing systems ( [3]; [4]), in parallel computing and computer pipelining ( [5]; [6]; [7]). Depending on the target application, different mathematical models exist, based on graph theory, mixed linear programming, Petri nets or (max, +) algebra.…”

Section: Introductionmentioning

confidence: 99%

A robust basic cyclic scheduling problem

Hamaz

Houssin

Cafieri

2018

EURO Journal on Computational Optimization

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This paper addresses the Basic Cyclic Scheduling Problem where the processing times are affected by uncertainties. We formulate the problem as a twostage robust optimization problem with polyhedral uncertainty set. We propose three exact algorithms for solving the problem. Two of them use a negative circuit detection algorithm as a subroutine and the last one is an Howard's algorithm adaptation. Results of numerical experiments on randomly generated instances show that the Howard's algorithm adaptation yields efficient results and opens perspectives on more difficult robust cyclic scheduling problems.

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Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit

Cited by 12 publications

References 16 publications

GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems

GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems

Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA

A robust basic cyclic scheduling problem

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