Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems

Abstract

Abstract-In the presence of radiation, particle strikes can cause temporary signal errors in ICs. Particle strikes that directly affect memory are known as single event upsets (SEUs), while strikes that affect combinational logic and spread to memory are called single event transients (SETs). In this paper, we propose two novel approaches to hardening integrated circuits against SEUs and SETs. The proposed approaches are fully-differential dual-interlocked storage cell (DICE) and triple path DICE (TPDICE).The fully-differential DICE and TPDICE approaches are compared against two existing approaches, which are triple modular redundancy (TMR) and basic SET-tolerant DICE. All approaches except for the basic SET-tolerant DICE scheme share a common theme, which is the ability to bypass SEUs and SETs. This is critical for performance, as it allows the system to proceed with subsequent operations while a cell is recovering from the effects of a particle strike. SET pulse widths can be substantial (up to 2 ns), and so high-performance systems cannot afford to pause operations while these pulses are present. The minimum clock periods obtained for the basic SET-tolerant approach were 515 ps with no SET, and 1310 ps with a 500 ps SET (in 0.18 m CMOS). In contrast, the clock periods for the bypass-capable approaches with no SET/500 ps SET were 628/749 ps for TMR, 348/480 ps for fully-differential DICE, and 434/552 ps for TPDICE. Among the approaches that bypass transient pulses, TPDICE is the most balanced. TMR suffers from overhead due to its need for external voting circuitry. In addition to this, fully-differential DICE cannot be used with combinational logic, while TPDICE can.

Soft error immune latch under SEU related double-node charge collection

“…However, the DICE latch has a partial DNCS-SEU tolerance [3], [20]. An enhanced alternative topology is TPDICE [21] where the four-stage DICE cell is extended to six stages. However, also this topology is not capable to provide full protection against DNCS-SEUs as there are scenarios without any hold node.…”

A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design

“…Well isolation, guard rings and layout techniques were utilized to solve the multiple upsets caused by charge sharing, but benefits of these techniques are quite limited [9,10]. In order to solve this severe problem, researchers have proposed plenty of latches which can effectively tolerate the DUs [11][12][13][14][15][16][17]. The latch designed in [12] employed a modified triple path dual-interlocked storage cell (TPDICE) [11] and Muller C-element (MCE), acquiring better tolerance.…”

“…In order to solve this severe problem, researchers have proposed plenty of latches which can effectively tolerate the DUs [11][12][13][14][15][16][17]. The latch designed in [12] employed a modified triple path dual-interlocked storage cell (TPDICE) [11] and Muller C-element (MCE), acquiring better tolerance. As for DNCS (Double-Node Charge Sharing) latch in [13] and CLCT (Circuit and Layout Combination Technique) latch in [14], both latches utilized interlocked structure and MCE to obtain the robustness.…”

Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories

“…Individual upsets that directly affect memory are known as Single Event Upsets (SEUs), while upsets that originate in logic are known as Single Event Transients (SETs). Many approaches have been designed to deal with SEUs and SETs [1]. However, most of these schemes cannot withstand multiple-node and Multiple-Bit Upsets (MBUs).…”