Schnelle Simulation des TI-TMS320C54x DSP

Pees, Stefan; Hoffmann, Andreas; Ropers, Andreas; Meyr, H.

doi:10.1524/itit.1999.41.2.32

Cited by 2 publications

(7 citation statements)

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“…Such compiled simulators for DSPs have been realized for specific processor architectures [Pees et al 1997]. Reusing the efforts for the implementation of the compiled techniques is extremely difficult because the compiled techniques are implemented in the simulation compiler, which is highly architecture dependent.…”

Section: Compiled Simulationmentioning

confidence: 99%

“…However, the instruction set model of the ARM 7 runs at more than 2 million instructions per second. Considering the results from [Pees et al 1997], we expect that using static simulation scheduling would even greatly improve this result.…”

Section: Simulation Speedmentioning

confidence: 99%

“…Compiled simulation of programmable DSP architectures was introduced to speed up the instruction-set simulation [Živojnović et al 1995] and was extended to cycle-accurate models of pipelined processors [Pees et al 1997]. So far, the approaches addressing the particular requirements of compiled simulation of DSPs are targeted to a specific processor architecture using a handwritten simulation compiler.…”

Section: Introductionmentioning

confidence: 99%

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Retargetable compiled simulation of embedded processors using a machine description language

Pees

Hoffmann

Meyr

2000

ACM Trans. Des. Autom. Electron. Syst.

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Fast processor simulators are needed for the software development of embedded processors, for HW/SW cosimulation systems, and for profiling and design of application-specific processors. Such fast simulators can be generated based on the machine description language LISA. Using this language to model processor architectures enables the generation of compiled simulators on various abstraction levels, assemblers, and compiler back ends. The article discusses the requirements of software development tools on processor models and presents the approach based on the LISA language. Furthermore, the implementation of a retargetable environment consisting of compiled simulator, debugger, and assembler is presented. Measurements for a verified, cycle-based LISA model of the TI TMS320C62x DSP show that this approach achieves between 37× and 170× higher simulation speed compared to a commercial simulator using a standard technique and the same accuracy level.

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Section: Compiled Simulationmentioning

confidence: 99%

Section: Simulation Speedmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Retargetable compiled simulation of embedded processors using a machine description language

Pees

Hoffmann

Meyr

2000

ACM Trans. Des. Autom. Electron. Syst.

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“…Compiled simulators for programmable architectures have been proven to outperform the commonly used interpretive simulators by roughly two orders in magnitude in speed without any loss in accuracy [10]. The principle of compiled simulation takes advantage from a priori knowlegde and moves frequent operations from simulation run-time to compile-time in order to provide the highest possible simulation speed.…”

Section: Introductionmentioning

confidence: 99%

“…Between fully compiled and fully interpretive simulation different levels of compiled simulation can be distguished, ranging from the mere compile-time instruction decoding up to compile-time scheduling for pipelined processor models (static scheduling). Such simulators have been realized for specific processor architectures [10].…”

Section: Introductionmentioning

confidence: 99%

Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description

Braun

Hoffmann

Nohl

et al. 2001

Proceedings of the 14th International Symposium on Systems Synthesis - ISSS '01

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Instruction set simulators are indispensable tools for both the design of programmable architectures and software development. However, due to a constantly increasing processor complexity and the frequent demand for cycle-accurate models, such simulators have become defectively slow. The principle of compiled simulation addresses this shortcoming. Compiled simulators make use of a priori knowlegde to accelerate simulation, with the highest efficieny achieved by employing static scheduling techniques.In the past, such statically scheduled simulators have only been implemented for specific DSP architectures. The approach presented here discusses the application of static scheduling techniques to retargetable simulation tools based on the processor description language LISA. Principles and implementation issues are discussed in this paper, and results are presented for two selected processor architectures.

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Schnelle Simulation des TI-TMS320C54x DSP

Cited by 2 publications

References 0 publications

Retargetable compiled simulation of embedded processors using a machine description language

Retargetable compiled simulation of embedded processors using a machine description language

Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description

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