Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description

Braun, Gunnar; Hoffmann, Andreas; Nohl, Achim; Meyr, H.

doi:10.1145/500001.500014

Cited by 21 publications

(13 citation statements)

References 19 publications

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“…Based on the results of the decoding phase the simulation compiler subsequently selects and sequences the appropriate host operations that are required to simulate the application. Since the time-consuming instruction scheduling is still performed at run-time (dynamically scheduled), statically scheduled [7] compiled simulators also move the instruction scheduling into the compilation phase. However, all compiled simulators rely on the assumption that the complete program code is known before the simulation starts and is furthermore run-time static.…”

Section: Compiled Simulationmentioning

confidence: 99%

A universal technique for fast and flexible instruction-set architecture simulation

Nohl¹,

Braun²,

Schliebusch³

et al. 2002

Proceedings of the 39th Conference on Design Automation - DAC '02

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100

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In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance is a key factor for the overall design efficiency. Based on the extremely poor performance of commonly used interpretive simulators, research work on fast compiled instruction-set simulation was started ten years ago. However, due to the restrictiveness of the compiled technique, it has not been able to push through in commercial products. This paper presents a new retargetable simulation technique which combines the performance of traditional compiled simulators with the flexibility of interpretive simulation. This technique is not limited to any class of architectures or applications and can be utilized from architecture exploration up to end-user software development. The work-flow and the applicability of the so-called just-intime cache compiled simulation (JIT-CCS) technique will be demonstrated by means of state of the art real world architectures.

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Section: Compiled Simulationmentioning

confidence: 99%

A universal technique for fast and flexible instruction-set architecture simulation

Nohl¹,

Braun²,

Schliebusch³

et al. 2002

Proceedings of the 39th Conference on Design Automation - DAC '02

Self Cite

100

View full text Add to dashboard Cite

show abstract

“…The static compiled method in [9] applies static scheduling techniques to retargetable simulation, improving simulation performance at the expense of flexibility. Compiled simulators were generated from model descriptions of TI's TMS320C54x (cycle accurate) and the ARM7 (instruction accurate) processors.…”

Section: Related Workmentioning

confidence: 99%

High Speed CPU Simulation Using LTU Dynamic Binary Translation

Jones

Topham

2009

High Performance Embedded Architectures and Compilers

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Abstract-Instruction set simulators are indispensable tools for exploring the design-space of innovative processor architectures, for processor verification, and for software development. Traditional interpretive simulators are too slow to cope with the increasing complexity of embedded processors now being deployed in many high performance systems. High speed emulation techniques based on dynamic binary translation have been proposed previously, but thus far we have not seen flexible multi-function full-system simulators capable of acting as golden reference models, software development platforms and designspace exploration tools. This paper presents a target-adaptable full-system simulator which combines the speed of JIT binary translation with the observability of interpreted simulation. We explain the mechanisms it uses to achieve sufficiently high performance to boot and run Linux interactively at speeds exceeding those achievable with FPGA-based RTL emulation of the same processor. We report performance figures from a set of representative embedded benchmarks which range from 187 to 373 MIPS. Our results also indicate that transient simulation speeds can exceed 1,000 MIPS, and we show that a full-system Linux simulation can sustain more than 148 MIPS.

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“…There has been an enormous body of work done on different classes of instruction-set simulators such as trace driven ( [14], [15]), interpretive ( [1], [2], [7]) and compiled simulators ( [3], [4], [5], [6], [12], [13]). While every simulator must deal with the address space mapping problem, to the best of our knowledge, very little has been reported that addresses this issue separately.…”

Section: Related Workmentioning

confidence: 99%

Memory access optimizations in instruction-set simulators

Reshadi

Mishra

2005

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simulators are widely used in embedded systems design. One of the key performance bottlenecks in interpretive simulation is the instruction and data memory access translation between host and target machines. The simulators must maintain and update the status of the simulated processor including memory and register values. A major challenge in the simulation is to efficiently map the target address space to the host address space. This paper presents two optimization techniques that aggressively utilize the spatial locality of the instruction and data accesses in interpretive simulation: signature based address mapping for optimizing general memory accesses; and incremental instruction fetch for optimizing instruction accesses. To demonstrate the utility of this approach we applied these techniques on SimpleScalar simulator, and obtained up to 30% performance improvement. Our techniques complement the recently proposed optimizations (JIT-CCS [1] and IS-CS [2]) and further improve the performance (up to 89%) on ARM7 and Sparc processors.

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Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description

Cited by 21 publications

References 19 publications

A universal technique for fast and flexible instruction-set architecture simulation

A universal technique for fast and flexible instruction-set architecture simulation

High Speed CPU Simulation Using LTU Dynamic Binary Translation

Memory access optimizations in instruction-set simulators

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