A universal technique for fast and flexible instruction-set architecture simulation

Nohl, Achim; Braun, Gunnar; Schliebusch, Oliver; Leupers, Rainer; Meyr, H.; Hoffmann, Andreas

doi:10.1145/513918.513927

Cited by 100 publications

(17 citation statements)

References 21 publications

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“…Therefore, the speed of a binary decoder can be very slow and may become a major performance bottleneck for speed-critical software tools such a s the instruction set simulators (ISSs). According to our experience and the results reported by other researchers [13], a slow decoder can affect the simulation speed of the ISSs by a factor of 2 to 4. An efficient binary decoder is thus highly desirable.…”

Section: Introductionsupporting

confidence: 57%

“…Such small decoders can easily fit into the cache of the host machine and have little impact on the performance of the applications using them. Such decoding cost is no higher than hand-coded decoders or the decoding cache in [13].…”

Section: Resultsmentioning

confidence: 99%

“…In a retargetable software tool development environment where a more general machine description language is used, it is a non-trivial task to derive such a well-organized specification, especially when the instruction set is irregular. [13] addresses the efficiency of binary decoding in ISS from a different angle. The proposed technique exploits the locality of the program under simulation by caching the decoding results for reuse.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Automated synthesis of efficient binary decoders for retargetable software toolkits

Wei¹,

Malik²

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

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A binary decoder is a common component of software development tools such as instruction set simulators, disassemblers and debuggers. The efficiency of the decoder can have a significant impact on the efficiency of these software tools. Automated synthesis of efficient binary decoders is therefore necessary for retargetable software tool development frameworks targeting the rapidly growing field of applicationspecific processor design. This paper describes a decoder synthesis algorithm that translates a simple instruction pattern specification into efficient binary decoders in C under given memory constraints. The algorithm constructs a decision tree with carefully chosen decoding primitives and cost models. As demonstrated through two case studies, the synthesized decoders achieve efficiency comparable to hand-coded decoders with ensured correctness. The algcrithm has no limitation on the input instruction patterns and it requires only the least amount of knowledge about the instruction encoding. Therefore it can be used with any machine description scheme containing instruction encoding information.

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Section: Introductionsupporting

confidence: 57%

Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Automated synthesis of efficient binary decoders for retargetable software toolkits

Wei¹,

Malik²

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

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“…SimpleScalar [8] is a retargetable simulator which supports various simulation accuracy levels, from functional to cycle-accurate. Nohl et al [15] and Lazarescu et al [9] propose a method which translates source programs to 978-1-4244-5767-0/10/$26.00 c2010 IEEE…”

Section: Related Workmentioning

confidence: 99%

Source-level timing annotation for fast and accurate TLM computation model generation

Lin¹,

Lo²,

Tsay³

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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This paper proposes a source-level timing annotation method for generation of accurate transaction level models for software computation modules. While Transaction Level Modeling (TLM) approach is widely adopted now for system modeling and simulation speed improvement, timing estimation accuracy often is compromised. To have reliable and accurate estimation results at system level, we propose a timing annotation method for accurate TLM computation model generation considering processor architecture with pipeline and cache structures, which are challenging but critical to accurate timing estimation. The experiments show that our results are within 2% of cycle accurate results and the approach is three orders faster than conventional ISS approaches.

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“…Some notable developments include compiled simulation [2], techniques that combine compiled and interpreted simulation [3,4], and automatic generation of optimized ISS components for steps such as instruction execution and instruction decoding [5,6]. The proposed work is largely complementary to, and can be combined with, the above techniques for instruction set simulation.…”

Section: Paper Contributions and Related Workmentioning

confidence: 99%

Hybrid simulation for embedded software energy estimation

Muttreja

Raghunathan

Ravi

et al. 2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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Software energy estimation is a critical step in the design of energyefficient embedded systems. Instruction-level simulation techniques, despite several advances, remain too slow for iterative use in systemlevel exploration. In this paper, we propose a methodology called hybrid simulation, which combines instruction set simulation with selective native execution (execution of some parts of the program directly on the simulation host computer), thereby overcoming the disadvantages of instruction-level simulation (low speed) and pure native execution (estimation accuracy, inapplicability to targetdependent code), while exploiting their advantages. Previously developed techniques for software energy macromodeling are utilized to estimate energy consumption for natively executed sub-programs. We identify and address the main challenges involved in hybrid simulation, and present an automatic tool flow for it, which analyzes a given program and selects functions for native execution in order to achieve maximum estimation efficiency while limiting estimation error. We have applied the proposed hybrid simulation methodology to a variety of embedded software programs, resulting in an average speed-up of 70% and estimation error of at most 6%, compared to one of the fastest publicly-available instruction set simulators.

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A universal technique for fast and flexible instruction-set architecture simulation

Cited by 100 publications

References 21 publications

Automated synthesis of efficient binary decoders for retargetable software toolkits

Automated synthesis of efficient binary decoders for retargetable software toolkits

Source-level timing annotation for fast and accurate TLM computation model generation

Hybrid simulation for embedded software energy estimation

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