SCPA: A Segemented Carry Prediction Approximate Adder Structure

Abstract

Approximate computing has excellent result in error-tolerant applications sacrificing computational accuracy for better performance in the area, speed, and power consumption. As the most basic operation, addition is used in a large number of applications in various occasions. Therefore it is of great importance to optimize the performance of addition computation. In this paper, a segemented carry prediction adder (SCPA) structure is proposed, which splits the long carry chain into several short chains for parallel computation. The design parameters are diversified by adjusting the size of the blocks and the prediction depth of each subadditive to achieve different levels of performance. Flexible parameter tuning allows different design goals to be achieved based on specific performance requirements, which makes SCPA a useful design guideline for approximate adders. The error performance of SCPA is mesured by MRED, NMRED, ER, and other indicators and significantly has the best statiscal performace compared to similar designs. The proposed design is synthesized under TSMC 65nm process, and the result shows that the SCPA has a very nice accuracy-power tradeoff under 8-bit and 16-bit condition.

Hardware Implementation of an Approximate Simplified Piecewise Linear Spiking Neuron

“…The adder merge result was then multiplied by the time parameter, and was then merged, to obtain the corresponding V n+1 for the current iteration. In this design, we used a segmented carry prediction adder (SCPA) [11] and a Pwl-Mit multiplier [12], as proposed earlier, to approximate the main calculations in the neuron, so as to further decrease the computation cost of the SPWL model.…”