“…The proposed design consists of D P1 , D P2 , D N1 , D N2 , D T1 , D T2 , and SCR. The four layers of P+, N-well, P-well, and N+ form a typical SCR device in low-voltage CMOS processes [10,11]. In this design, the stacked diodes from I/O to V DD (D P1 and D P2 ) and from V SS to I/O (D N1 and D N2 ) perform the ESD current paths of I/O-to-V DD and V SS -to-I/O, respectively.…”