SCRIMP: A General Stochastic Computing Architecture using ReRAM in-Memory Processing

Gupta, Saransh; Imani, Mohsen; Sim, Joonseop; Huang, Andrew; Wu, Fan; Najafi, M. Hassan; Rosing, Tajana

doi:10.23919/date48585.2020.9116338

Cited by 10 publications

(3 citation statements)

References 33 publications

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“…PIM Bitwise Operations: BitNAP utilizes switching based PIM operations to implement bitwise operations in memory. The work in [21][22][23] implements different logic gates like NOR, NAND, OR, XNOR, etc in the digital memory. Figure 2a explains the execution proposed in [22] where, by applying a voltage, 0 , at the input devices and grounding the output device, many bitwise operations are performed.…”

Section: Bitnap Block Computationmentioning

confidence: 99%

Implementing binary neural networks in memory with approximate accumulation

Gupta

Imani

Zhao

et al. 2020

Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

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Processing in-memory (PIM) has shown great potential to accelerate the inference tasks of binarized neural networks (BNNs) by reducing data movement between processing units and memory. However, existing PIM architectures require analog/mixed-signal circuits that do not scale with the CMOS technology. On the contrary, we propose BitNAP (Binarized neural network acceleration with in-memory ThreSholding), which performs optimization at operation, peripheral, and architecture levels for an efficient BNN accelerator. BitNAP supports row-parallel bitwise operations in crossbar memory by exploiting the switching of 1-bit bipolar resistive devices and a unique hybrid tunable thresholding operation. In order to reduce the area overhead of sensing-based operations, BitNAP presents a memory sense amplifier sharing scheme and also, a novel operation pipelining to reduce the latency overhead of sharing. We evaluate the efficiency of BitNAP on the MNIST and ImageNet datasets using popular neural networks. BitNAP is on average 1.24× (10.7×) faster and 185.6× (10.5×) more energyefficient as compared to the state-of-the-art PIM accelerator for simple (complex) networks. CCS CONCEPTS • Hardware → Emerging architectures; Non-volatile memory; • Computer systems organization → Neural networks.

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Section: Bitnap Block Computationmentioning

confidence: 99%

Implementing binary neural networks in memory with approximate accumulation

Gupta

Imani

Zhao

et al. 2020

Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

Self Cite

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“…P. Knag et al proposed a method where analog input data was converted to a series of programming pulses with variable pulse widths and applied to an array of memristive memory cells [33]. The method proposed by S. Gupta et al exploited the stochastic behavior of ReRAM devices to generate stochastic bit-streams in parallel over multiple rows [34]. M. Riahi Alam et al took a slightly different approach where logic-in-memory architectures were used to convert binary data into deterministic bit-streams [35].…”

Section: Introductionmentioning

confidence: 99%

A Stochastic Computing Scheme of Embedding Random Bit Generation and Processing in Computational Random Access Memory (SC-CRAM)

Zink

Zabihi

et al. 2023

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Stochastic computing (SC) has emerged as a promising solution for performing complex functions on large amounts of data to meet future computing demands. However, the hardware needed to generate random bit-streams using conventional CMOS based technologies drastically increases the area and delay cost. Area costs can be reduced using spintronics based RNGs, however, this will not alleviate the delay costs since stochastic bit generation is still performed separately from the computation. In this paper, we present an SC method of embedding stochastic bit generation and processing in a computational random access memory array, which we refer to as SC-CRAM. We demonstrate that SC-CRAM is a resilient and low cost method for image processing, Bayesian inference systems, and Bayesian belief networks.

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“…A signiicant portion of the total processing time and the total energy consumption is wasted on 1) reading the data from memory, 2) transferring the data between memory and processing unit, and 3) writing the result back into the memory [7] [30] [53] [32] [63]. In-Memory Computation (IMC) or Processing in Memory (PIM) is an emerging computational approach that ofers the ability to both store and process data within memory cells [5,26,27,52,60,62,66,69]. This technique eliminates the high overhead of transferring data between memory and processing unit, improving the performance and reducing the energy consumption by processing data in memory.…”

Section: Introductionmentioning

confidence: 99%

Sorting in Memristive Memory

Alam

Najafi

TaheriNejad

2022

J. Emerg. Technol. Comput. Syst.

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Sorting data is needed in many application domains. Traditionally, the data is read from memory and sent to a general-purpose processor or application-specific hardware for sorting. The sorted data is then written back to the memory. Reading/writing data from/to memory and transferring data between memory and processing unit incur significant latency and energy overhead. In this work, we develop the first architectures for in-memory sorting of data to the best of our knowledge. We propose two architectures. The first architecture is applicable to the conventional format of representing data, i.e., weighted binary radix. The second architecture is proposed for developing unary processing systems, where data is encoded as uniform unary bit-streams. As we present, each of the two architectures has different advantages and disadvantages, making one or the other more suitable for a specific application. However, the common property of both is a significant reduction in the processing time compared to prior sorting designs. Our evaluations show on average 37 × and 138 × energy reduction for binary and unary designs, respectively, compared to conventional CMOS off-memory sorting systems in a 45nm technology. We designed a 3 × 3 and a 5 × 5 Median filter using the proposed sorting solutions, which we used for processing 64 × 64 pixel images. Our results show a reduction of 14 × and 634 × in energy and latency, respectively, with the proposed binary, and 5.6 × and 152 × 10 3 in energy and latency with the proposed unary approach compared to those of the off-memory binary and unary designs for the 3 × 3 Median filtering system.

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SCRIMP: A General Stochastic Computing Architecture using ReRAM in-Memory Processing

Cited by 10 publications

References 33 publications

Implementing binary neural networks in memory with approximate accumulation

Implementing binary neural networks in memory with approximate accumulation

A Stochastic Computing Scheme of Embedding Random Bit Generation and Processing in Computational Random Access Memory (SC-CRAM)

Sorting in Memristive Memory

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