SDNoC: Software defined network on a chip

Berestizshevsky, Konstantin; Even, Guy; Fais, Yaniv; Ostrometzky, Jonatan

doi:10.1016/j.micpro.2017.03.005

Cited by 22 publications

(26 citation statements)

References 9 publications

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“…This work is more in line with our proposed architecture, and, despite its good scalability, the evaluation on the area consumption is lacking. In [26], the authors proposed a hybrid software-hardware NoC architecture. In contrast to conventional NoCs, the control plane is implemented as a software module running on a dedicated core.…”

Section: System Overviewmentioning

confidence: 99%

Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud

Scionti

Mazumdar

Portero

2018

Sensors

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The rapid evolution of Cloud-based services and the growing interest in deep learning (DL)-based applications is putting increasing pressure on hyperscalers and general purpose hardware designers to provide more efficient and scalable systems. Cloud-based infrastructures must consist of more energy efficient components. The evolution must take place from the core of the infrastructure (i.e., data centers (DCs)) to the edges (Edge computing) to adequately support new/future applications. Adaptability/elasticity is one of the features required to increase the performance-to-power ratios. Hardware-based mechanisms have been proposed to support system reconfiguration mostly at the processing elements level, while fewer studies have been carried out regarding scalable, modular interconnected sub-systems. In this paper, we propose a scalable Software Defined Network-on-Chip (SDNoC)-based architecture. Our solution can easily be adapted to support devices ranging from low-power computing nodes placed at the edge of the Cloud to high-performance many-core processors in the Cloud DCs, by leveraging on a modular design approach. The proposed design merges the benefits of hierarchical network-on-chip (NoC) topologies (via fusing the ring and the 2D-mesh topology), with those brought by dynamic reconfiguration (i.e., adaptation). Our proposed interconnect allows for creating different types of virtualised topologies aiming at serving different communication requirements and thus providing better resource partitioning (virtual tiles) for concurrent tasks. To further allow the software layer controlling and monitoring of the NoC subsystem, a few customised instructions supporting a data-driven program execution model (PXM) are added to the processing element’s instruction set architecture (ISA). In general, the data-driven programming and execution models are suitable for supporting the DL applications. We also introduce a mechanism to map a high-level programming language embedding concurrent execution models into the basic functionalities offered by our SDNoC for easing the programming of the proposed system. In the reported experiments, we compared our lightweight reconfigurable architecture to a conventional flattened 2D-mesh interconnection subsystem. Results show that our design provides an increment of the data traffic throughput of 9.5% and a reduction of 2.2× of the average packet latency, compared to the flattened 2D-mesh topology connecting the same number of processing elements (PEs) (up to 1024 cores). Similarly, power and resource (on FPGA devices) consumption is also low, confirming good scalability of the proposed architecture.

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Section: System Overviewmentioning

confidence: 99%

Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud

Scionti

Mazumdar

Portero

2018

Sensors

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“…Recent research showed the Software-Defined Networking (SDN) benefits for MCSoCs, targeting energy reduction and QoS [7]- [9]. The SDN paradigm reduces the Networkon-Chip (NoC) physical complexity by moving the router control logic from the hardware to the software level.…”

Section: Introductionmentioning

confidence: 99%

SDN-Based Secure Application Admission and Execution for Many-Cores

2020

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General-purpose many-core system-on-chip (MCSoC) requires support to the execution of dynamic workloads, i.e., admission of new applications at runtime. Some applications may require QoS and security from the MCSoC, not tolerating that malicious tasks or hardware Trojans steal or corrupts their data. A robust method to provide security is to isolate the communication and computation. Most current works employ such isolation in continuous regions named secure zones (SZ). Motivated by the recent study of the Software-Defined Networking (SDN) paradigm for MCSoCs, this work proposes to use SDN-based management to implement the communication isolation at runtime. The computation isolation occurs by mapping only tasks of the same application at each core. The communication isolation is supported by the SDN paradigm, which establishes dedicating paths for secure applications. Results show that the SDN-based approach presents a negligible latency to admit and execute a secure application, with a reduced hardware cost and higher computational resources utilization compared to SZs.

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“…Thereafter Scionti et al [9] use the SDN architecture in order to explore dynamic changes in the network topology; each Processing Element (PE) has specific instructions to control the network topology by software, including switch off the links which are not used. Another interesting approach is proposed by Berestizshevsky et al [10], in which an SDNoC strategy by implementing a network manager is introduced, acting as controller with global view of the network, which controls the network in adaptive manner. However in order to be deployed on chip, a detailed API implementation and standardization between control plane and data forwarding plane need to be considered.…”

Section: Introductionmentioning

confidence: 99%

SSPSoC: A Secure SDN-Based Protocol over MPSoC

Ellinidou

Sharma

Rigas

et al. 2019

Security and Communication Networks

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In recent years, Multi-Processor System-on-Chips (MPSoCs) are widely deployed in safety-critical embedded systems. The Cloud-of-Chips (CoC) is a scalable MPSoC architecture comprised of a large number of interconnected Integrated Circuits (IC) and Processing Clusters (PC) destined for critical systems. While many researches have focused on addressing the hardware issues of MPSoCs, the communication over them has not been very well explored. Following the SDN concept, we propose a new protocol in order to secure the communication and efficiently manage the routing within the CoC. The SSPSoC includes a private key derivation phase, a group key agreement (GKA) phase, and a data exchange phase in order to ensure that basic security primitives are preserved and provide secure communication. Furthermore, a network of 1-30 nodes is set in order to validate the proposed protocol and measure the network performance and memory consumption of the proposed protocol.

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SDNoC: Software defined network on a chip

Cited by 22 publications

References 9 publications

Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud

Towards a Scalable Software Defined Network-on-Chip for Next Generation Cloud

SDN-Based Secure Application Admission and Execution for Many-Cores

SSPSoC: A Secure SDN-Based Protocol over MPSoC

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