Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test Generation

Chandrasekar, Maheshwar; Rahagude, Nikhil; Hsiao, Michael S.

doi:10.1007/s10836-010-5142-2

Cited by 8 publications

(4 citation statements)

References 27 publications

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“…For each fault pair, we add a constraint to ensure that at least one of the faults is excited. In the running example, if fault f 1 is injected in the 4 th copy of the circuit and fault f 2 is injected in the 6 th copy of the circuit, then the excitation constraint added will be g1 [4] = 1 || g2 [6] = 0…”

Section: B Excitation Constraintmentioning

confidence: 99%

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A SMT-based diagnostic test generation method for combinational circuits

Prabhu

Hsiao

Lingappan

et al. 2012

2012 IEEE 30th VLSI Test Symposium (VTS)

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A diagnostic test pattern generator using a Satisfiability Modulo Theory (SMT) solver is proposed. Rather than targeting a single fault pair at a time, the proposed SMT approach can distinguish multiple fault pairs in a single instance. Several heuristics are proposed to constrain the SMT formula to further reduce the search space, including fault selection, excitation constraint, reduced primary output vector, and coneof-influence reduction. Experimental results for the ISCAS85 and full-scan versions of ISCAS89 benchmark circuits show that fewer diagnostic vectors are generated compared with conventional diagnostic test generation methods. Up to 73% reduction in the number of vectors generated can be achieved in large circuits.Index Terms-Satisfiability Modulo theory(SMT); fault distinguishing; diagnostic test pattern generation;

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Section: B Excitation Constraintmentioning

confidence: 99%

“…of faults. In [6], an incremental learning-based ADPG flow was proposed which incrementally utilized the information learned during ATPG for ADPG. An output dependent approach for diagnostic test generation was proposed in [7] in which outputs of the circuit are considered one at a time.…”

Section: Introductionmentioning

confidence: 99%

A SMT-based diagnostic test generation method for combinational circuits

Prabhu

Hsiao

Lingappan

et al. 2012

2012 IEEE 30th VLSI Test Symposium (VTS)

Self Cite

View full text Add to dashboard Cite

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“…These ‗X' bits can also be filled to increase the diagnostic ability of the test set. References [6], [9][10][11] provide X-filling algorithms for diagnosis purposes. In [6] and [9] authors have used the test sets with ‗X' bits to maximize the diagnostic power of the test set by applying ‗X' bit filling algorithms to maximize the metric proposed in [6].…”

Section: Introductionmentioning

confidence: 99%

“…In [6] authors have proposed a simple FS (Flip-Select heuristic) for ‗X' bit filling. The work [9] proposes a GA (genetic Algorithm) for ‗X' bit filling and also it has been shown that the performance of these filling techniques are superior to the methods proposed in [10] and [11].…”

Section: Introductionmentioning

confidence: 99%

Test set customization for improved fault diagnosis without sacrificing coverage

Nuthakki

Chattopadhyay

Chakraborty

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Diagnosis is extremely important to ramp up the yield during the integrated circuit manufacturing process. It reduces the time to market and product cost. The back bone of any diagnosis algorithm is the test set in use. In this paper, a novel method has been proposed to increase the diagnosability of a given test set. The proposed method, which takes as input a test set generated for high fault coverage, is capable of increasing the diagnostic power of the test set without affecting its fault coverage. It is able to achieve this with either no or small increase in number of patterns. The crux of the method lies in introducing test patterns having 'X' bits into the test set without changing its coverage, and using a 'X' bit filling algorithm to maximize its diagnostic power.

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An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets

Nuthakki

Chattopadhyay

2015

2015 IEEE 24th Asian Test Symposium (ATS)

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Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test Generation

Cited by 8 publications

References 27 publications

A SMT-based diagnostic test generation method for combinational circuits

A SMT-based diagnostic test generation method for combinational circuits

Test set customization for improved fault diagnosis without sacrificing coverage

An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets

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