Secure and Fast Implementation of ARX-Based Block Ciphers Using ASIMD Instructions in ARMv8 Platforms

Song, JinGyo; Seo, Seog Chung

doi:10.1109/access.2020.3032785

Cited by 3 publications

(46 citation statements)

References 17 publications

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“…We propose parallel implementation of ARX-based block ciphers (LEA, HIGHT, and revised CHAM) by utilizing the NEON engine in ARMv8 architecture. The proposed parallel technique is more efficient than the existing data parallel processing techniques in [9,10]. In LEA and revised CHAM, we eliminate the transpose operations required to apply data parallelism through LD4 and ST4 instructions when loading data from memory to four vector registers and storing data from four vector registers into memory.…”

Section: Proposing the Efficient Data Parallelism Of Arx-based Block Ciphersmentioning

confidence: 99%

“…In the NEON engine, parallel processing is possible to 64, 32, 16, and 8-bit wise depending on the lane within the 128-bit vector register. Until now, works on parallel optimization of various block ciphers utilizing the NEON engine in ARMv7 and ARMv8 architecture have been conducted [9,10,[18][19][20]. Table 4 shows the number of simultaneously performed encryptions utilizing the NEON engine in related works.…”

Section: Related Work Parallel Implementation Of Block Ciphers On Neon Engine and Ctr Mode Optimizationmentioning

confidence: 99%

“…Through the 4-way MixColumns, the authors achieved improved performance in MixColumns. In IEEE ACCESS'20 [10], the authors proposed secure and fast implementation of HIGHT and CHAM by utilizing the NEON engine in ARMv8 platforms. In the HIGHT and revised CHAM' fast implementation, data and task parallelism was effectively applied to process multiple operations and data simultaneously.…”

Section: Related Work Parallel Implementation Of Block Ciphers On Neon Engine and Ctr Mode Optimizationmentioning

confidence: 99%

“…Through the above process, 16 encryptions can be performed simultaneously in a total of eight vector registers. In the existing work [10], only 24 encryptions were processed simultaneously on the NEON engine, but we process 48 encryptions simultaneously by efficiently utilizing all vector registers. Figure 9 shows register scheduling for the proposed parallel implementation of HIGHT.…”

Section: Hight Optimizationmentioning

confidence: 99%

“…Require: v0-v7(Plaintexts) Ensure: v0-v7(Ciphertexts) Algorithm 3 is a round function to which a data parallelism technique is applied in HIGHT. In the HIGHT optimization of [10], both task and data parallelism technique are applied, but Algorithm 3 applies only a data parallelism technique. Our contribution of Algorithm 3 is a data parallelism technique for HIGHT.…”

Section: Algorithm 2 Efficient Transpose Operation For Hightmentioning

confidence: 99%

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Efficient Parallel Implementation of CTR Mode of ARX-Based Block Ciphers on ARMv8 Microcontrollers

Song

Seo

2021

Applied Sciences

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With the advancement of 5G mobile telecommunication, various IoT (Internet of Things) devices communicate massive amounts of data by being connected to wireless networks. Since this wireless communication is vulnerable to hackers via data leakage during communication, the transmitted data should be encrypted through block ciphers to protect the data during communication. In addition, in order to encrypt the massive amounts of data securely, it is essential to apply one of secure mode of operation. Among them, CTR (CounTeR) mode is the most widely used in industrial applications. However, these IoT devices have limited resources of computing and memory compared to typical computers, so that it is challenging to process cryptographic algorithms that have computation-intensive tasks in IoT devices at high speed. Thus, it is required that cryptographic algorithms are optimized in IoT devices. In other words, optimizing cryptographic operations on these IoT devices is not only basic but also an essential effort in order to build secure IoT-based service systems. For efficient encryption on IoT devices, even though several ARX (Add-Rotate-XOR)-based ciphers have been proposed, it still necessary to improve the performance of encryption for smooth and secure IoT services. In this article, we propose the first parallel implementations of CTR mode of ARX-based ciphers: LEA (Lightweight Encryption Algorithm), HIGHT (high security and light weight), and revised CHAM on the ARMv8 platform, a popular microcontroller in various IoT applications. For the parallel implementation, we propose an efficient data parallelism technique and register scheduling, which maximizes the usage of vector registers. Through proposed techniques, we process the maximum amount of encryption simultaneously by utilizing all vector registers. Namely, in the case of HIGHT and revised CHAM-64/128 (resp. LEA, revised CHAM-128/128, and CHAM-128/256), we can execute 48 (resp. 24) encryptions simultaneously. In addition, we optimize the process of CTR mode by pre-computing and using the intermediate value of some initial rounds by utilizing the property that the nonce part of CTR mode input is fixed during encryptions. Through the pre-computation table, CTR mode is optimized up until round 4 in LEA, round 5 in HIGHT, and round 7 in revised CHAM. With the proposed parallel processing technique, our software provides 3.09%, 5.26%, and 9.52% of improved performance in LEA, HIGHT, and revised CHAM-64/128, respectively, compared to the existing parallel works in ARM-based MCU. Furthermore, with the proposed CTR mode optimization technique, our software provides the most improved performance with 8.76%, 8.62%, and 15.87% in LEA-CTR, HIGHT-CTR, and revised CHAM-CTR, respectively. This work is the fastest implementation of CTR mode on ARMv8 architecture to the best of our knowledge.

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Section: Proposing the Efficient Data Parallelism Of Arx-based Block Ciphersmentioning

confidence: 99%

Section: Related Work Parallel Implementation Of Block Ciphers On Neon Engine and Ctr Mode Optimizationmentioning

confidence: 99%

Section: Related Work Parallel Implementation Of Block Ciphers On Neon Engine and Ctr Mode Optimizationmentioning

confidence: 99%

Section: Hight Optimizationmentioning

confidence: 99%

Section: Algorithm 2 Efficient Transpose Operation For Hightmentioning

confidence: 99%

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Efficient Parallel Implementation of CTR Mode of ARX-Based Block Ciphers on ARMv8 Microcontrollers

Song

Seo

2021

Applied Sciences

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High-Speed Fault Attack Resistant Implementation of PIPO Block Cipher on ARM Cortex-A

2021

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In ICISC'20 conference, PIPO (Plug-In and Plug-Out) was proposed as an efficient block cipher for secure communication in IoT (Internet of Things) environment. Although PIPO equips easily high-order masking implementation because of small non-linear operations and short rounds, PIPO is still vulnerable to fault attack. For resisting the fault attack, block cipher implementation should be applied to the fault attack countermeasure. However, these techniques make the performance of computationallyintensive cryptographic algorithms slower in constrained devices. To improve this, we propose the first fast and secure software of PIPO block cipher co-designed with ARM/NEON processor for high-speed secure communication. For accelerating the performance, we present an optimal implementation of PIPO block cipher in ARM/NEON processor, respectively, and design the Interleaved way utilizing two cores. With the proposed optimal techniques, we provide the high-speed secure software. In addition, we present an interleaving random-shuffling technique, which optimizes random-shuffling by utilizing two cores. For ensuring the resistance of fault attacks, we validated the fault resistance with the computation and instruction fault model. We utilize the intra-instruction-redundancy and known ciphertext to detect them. Through the proposed contributions, the fast software for PIPO block cipher achieves the fastest performance than previous related studies. The secure software with the fault countermeasures is nearly 3 times faster than the reference implementation without any fault attack countermeasures. In addition, our secure software achieved performance improvement of 301% and 463% compared to the existing best work (HIGHT and revised CHAM). As a result, our fast and secure software for PIPO block cipher achieved the fastest performance by co-designing with two cores compared to previous work that is utilized only one core. Our software can be utilized for high-speed encrypted communication and CTR-DRBG in ARMv8-based IoT devices.

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A Comparative Study of Post-Quantum Cryptographic Algorithm Implementations for Secure and Efficient Energy Systems Monitoring

Satrya,

Agus,

Mnaouer

2023

Electronics

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The Internet of Things (IoT) has assumed a pivotal role in the advancement of communication technology and in our daily lives. However, an IoT system such as a smart grid with poorly designed topology and weak security protocols might be vulnerable to cybercrimes. Exploits may arise from sensor data interception en route to the intended consumer within an IoT system. The increasing integration of electronic devices interconnected via the internet has galvanized the acceptance of this technology. Nonetheless, as the number of users of this technology surges, there must be an aligned concern to ensure that security measures are diligently enforced within IoT communication systems, such as in smart homes, smart cities, smart factories, smart hospitals, and smart grids. This research addresses security lacunae in the topology and configuration of IoT energy monitoring systems using post-quantum cryptographic techniques. We propose tailored implementations of the Rivest–Shamir–Adleman (RSA), N-th degree Truncated Polynomial Ring Units (NTRU), and a suite of cryptographic primitives based on Module Learning With Rounding (Saber) as post-quantum cryptographic candidate algorithms for IoT devices. These aim to secure publisher–subscriber end-to-end communication in energy system monitoring. Additionally, we offer a comparative analysis of these tailored implementations on low-resource devices, such as the Raspberry Pi, during data transmission using the Message Queuing Telemetry Transport (MQTT) protocol. Results indicate that the customized implementation of NTRU outperforms both SABER and RSA in terms of CPU and memory usage, while Light SABER emerges as the front-runner when considering encryption and decryption delays.

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Secure and Fast Implementation of ARX-Based Block Ciphers Using ASIMD Instructions in ARMv8 Platforms

Abstract: This report is a result that was implemented as a research project on efficient implementation of approved algorithm in Korean Cryptographic Module Validation Program (No. 2020-060) by the affiliated institute of ETRI.

Cited by 3 publications

References 17 publications

Efficient Parallel Implementation of CTR Mode of ARX-Based Block Ciphers on ARMv8 Microcontrollers

Efficient Parallel Implementation of CTR Mode of ARX-Based Block Ciphers on ARMv8 Microcontrollers

High-Speed Fault Attack Resistant Implementation of PIPO Block Cipher on ARM Cortex-A

A Comparative Study of Post-Quantum Cryptographic Algorithm Implementations for Secure and Efficient Energy Systems Monitoring

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