Security Network On-Chip for Mitigating Side-Channel Attacks

Kenarangi, Farid; Partin-Vaisband, Inna

doi:10.1109/slip.2019.8771328

Cited by 3 publications

(5 citation statements)

References 12 publications

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“…Within the scope of this study, the impacts of hyper-parameters on DLSCA's efficiency have not been thoroughly investigated. This is because Proof et al [20] address VGG hyper-parameter selection in great detail. This is the primary explanation for this.…”

Section: Resultsmentioning

confidence: 99%

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Design of Deep Learning Techniques for Side-Channel Attacks on Masked 128-bit AES Implementations

Saeb Nahi,

Fattah,

Mutashar

et al. 2024

KJCS

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Researchers are exploring the use of convolutional neural networks (CNNs) in side-channel attacks to understand the weaknesses in cryptographic implementation. CNNs can learn hierarchical characteristics automatically from electromagnetic radiation or power usage during cryptographic processes. Researchers train CNNs on side-channel data to extract meaningful representations and deduce secret keys. Deep learning algorithms are helpful in evaluating the security of embedded systems, and CNNs are a feasible paradigm for profiling side-channel analysis attacks. In this paper, it has been introduced a VGG (Visual Geometry Group)-Net architecture, which is a typical deep convolutional neural network design with numerous layers. It uses the ASCAD dataset to conduct experiments. They found that VGG-Net architecture Side Channel Attacks (SCA) provides better results than the previously optimized CNN model by significantly reducing the number of side-channel traces required for successful attacks on desynchronized datasets. The researchers also discovered that synchronous traces serve as the pre-training source for VGG-Net architecture, functioning successfully in terms of jittering with minimal fine-adjusting after training

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Section: Resultsmentioning

confidence: 99%

“…Furthermore, the DDLA attack is fully capable of extracting the secret key of the disguised AES implementation when the epoch value is 10 or higher. This is particularly true when the epoch value is larger than 10 [20].…”

Section: Review Of Workmentioning

confidence: 95%

Design of Deep Learning Techniques for Side-Channel Attacks on Masked 128-bit AES Implementations

Saeb Nahi,

Fattah,

Mutashar

et al. 2024

KJCS

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“…Several significant achievements in HT detection have been demonstrated with machine learning (ML) approaches. Based on an extensive literature review in the recent survey on ML against HT attacks [7], several ML-based HT detection methods focus on sidechannel analysis because large volumes of side-channel data can be produced and utilized for training [8], [9]. However, these methods require a golden HT-free model to compare the reference side-channel data with the information obtained from the chip under investigation.…”

Section: Review Of Existing Ht Early Detection Methodsmentioning

confidence: 99%

“…Finally, tagged data is sampled (7) into a perception field feature array using the embeddings and graph information. The perception field of each embedding is then classified ( 8) with a supervised model, and the per-embedding predictions are aggregated (9) according to the preferred detection policy. Using a zero-tolerance detection policy, the overall IC is labeled as compromised if an HT embedding is detected.…”

Section: Proposed Frameworkmentioning

confidence: 99%

Netwise Detection of Hardware Trojans Using Scalable Convolution of Graph Embedding Clouds

Utyamishev,

Partin-Vaisband

2024

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Hardware Trojans (HTs) are malicious circuits that can be inserted into integrated circuits (ICs) during the design, manufacturing, or packaging phases. HTs can cause a variety of security and safety problems, such as data theft, denialof-service attacks, and physical damage. A scalable referencefree framework is introduced in this paper for netwise gatelevel detection of existing and unknown HTs. The proposed framework consists of embedding-based automated netlist graph analysis and a supervised convolution-based classification of the individual IC net embeddings. A novel convolution algorithm for learning embedded IC graphs has been developed to overcome fundamental scalability limitation of existing graph convolutional neural networks. The performance of the proposed framework is experimentally demonstrated based on the TrustHub TRIT-TC benchmark suite, yielding a high recall of 96% and a precision of 86% for the netwise detection. The individual HT-compromised nets are highlighted within less than 0.1 seconds in >17, 000gate ICs. The proposed framework provides a scalable way to detect existing and unknown HTs without relying on HT-free reference ICs and can be effectively applied to large complex modern ICs. The unique combination of these characteristics makes the proposed framework more practical for real-world hardware cybersecurity applications as compared with prior art.

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“…Despite the fact that the number of devices is growing, this is also producing security problems and vulnerabilities, which is boosting the need for solutions that have been certified. As a consequence of this, millions of things are put through rigorous security examinations on a daily basis in evaluation labs located all over the world [2]. Since the 1990s, field study in cryptography and information security have conducted substantial study on side-channel attacks (SCA), also known as analyses.…”

Section: Introductionmentioning

confidence: 99%

Design of Deep Learning Technique Based Side Channel Attack Analysis for System on Chips

Fattah

2024

IJPS

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The effectiveness of deep learning techniques has increased in recent years, making it possible to assess side channel attacks on System-on-Chips (SoCs). Specifically, this is due to the fact that they provide a sophisticated method to capitalise on the unintended loss of information that occurs during cryptographic procedures. In this particular scenario, it is very necessary to collect information on side channels, such as power consumption or electromagnetic emissions. There is a procedure called as preprocessing that involves cleaning and modifying the raw data in order to make it more acceptable for input into neural networks. The specifics of the side channel information are what define whether or not a deep learning architecture, such as Recurrent Neural Networks (RNNs), Long Short-Term Memory (LSTM) networks, or other specialist structures, should be used. Following this, the architecture of the model is painstakingly created, consisting of layers, units, and activation functions, with the purpose of effectively collecting and deciphering the intricate patterns that are associated with the processing of sensitive data on the SOC.As part of this study, we presented a CNN-dependent profiled SCA assault that was directed against an AES cypher that was operating on a SoC. During the phase of setup, we focus on the discharge from a minor capacitor that is linked with the principal line of power supply. This capacitor produces a distinct signal, and we do not capture electromagnetic emission of chip surface. When it comes to the matching and profiling phases, CNN is then used. In light of the fact that the most recent AES round did not uncover any leaks, it is recommended that a novel approach be used in order to retrieve the keys from the first round, Through the use of AES algorithm observations, we were able to develop a differential equation that included the selected intermediate value and basic text. This equation in the end resulted in possibility of advantageous for incorrect value.

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Security Network On-Chip for Mitigating Side-Channel Attacks

Cited by 3 publications

References 12 publications

Design of Deep Learning Techniques for Side-Channel Attacks on Masked 128-bit AES Implementations

Design of Deep Learning Techniques for Side-Channel Attacks on Masked 128-bit AES Implementations

Netwise Detection of Hardware Trojans Using Scalable Convolution of Graph Embedding Clouds

Design of Deep Learning Technique Based Side Channel Attack Analysis for System on Chips

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