SEFI cross-section evaluation by fault injection software approach and hardware detection

Loskutov, I.O.; Nekrasov, Pavel V.; Shvetsov-Shilovskiy, Ivan I.; Boychenko, Dmitry V.; Uzhegov, V.M.

doi:10.1109/miel.2017.8190114

Cited by 6 publications

(4 citation statements)

References 12 publications

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“…Among all the errors induced by fault injection, single-event functional interrupts at the system level (systems-on-chips -SoC) are undoubtedly the most difficult to characterize and to model because: i) these errors can have multiple causes and ii) during SEFIs the system can behave unpredictably [157]. Usually, SEFIs appear as a spontaneous system reset, a program execution stop (hang-up) or an upset in program execution that can be only repaired by external reset [158]. It is known that SEFIs are caused by upsets in program or data memory (critical bits) or transients and interference on internal lines or peripherical circuitry [158].…”

Section: High-level Description At System Levelmentioning

confidence: 99%

“…Usually, SEFIs appear as a spontaneous system reset, a program execution stop (hang-up) or an upset in program execution that can be only repaired by external reset [158]. It is known that SEFIs are caused by upsets in program or data memory (critical bits) or transients and interference on internal lines or peripherical circuitry [158]. Recent studies have also shown that increasing complexity and size of program code, as well as real-time operating system usage, leads to a higher probability of SEFIs that directly affects the reliability of a modern SoCs [159].…”

Section: High-level Description At System Levelmentioning

confidence: 99%

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Multiscale, Multiphysics Modeling and Simulation of Single-Event Effects in Digital Electronics: From Particles to Systems

Autran,

Munteanu

2024

IEEE Trans. Nucl. Sci.

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This review paper aims to provide a survey of modeling and simulation of single-event effects (SEEs) in digital electronics at device, circuit and system levels. It primarily focuses on the specific multi-scale, multi-physics, multi-domain nature of SEEs and on the main underlying physical mechanisms that lead to the occurrence of single events in digital devices and circuits. This review addresses the different ways to model and simulate both in space and time this complex sequence of mechanisms from the particle-material interaction up to the electrical response of a given electronics device, circuit, or system. It highlights the specific features of each methodology, and discusses simulation requirements, code or model inputs and expected outputs.

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Section: High-level Description At System Levelmentioning

confidence: 99%

Section: High-level Description At System Levelmentioning

confidence: 99%

Multiscale, Multiphysics Modeling and Simulation of Single-Event Effects in Digital Electronics: From Particles to Systems

Autran,

Munteanu

2024

IEEE Trans. Nucl. Sci.

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“…The authors of [15] proposed a detailed analysis and hardening architecture based on lockstep synchronization supporting FreeRTOS. The heavy ion irradiation test presented in [16] targets the SRAM and the special purpose registers of an ARM microcontroller to evaluate the impact of the radiation-induced SEU.…”

Section: Related Workmentioning

confidence: 99%

Exploring the Impact of Soft Errors on the Reliability of Real-Time Embedded Operating Systems

et al. 2022

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The continuous scaling of electronic components has led to the development of high-performance microprocessors that are suitable even for safety-critical applications where radiation-induced errors such as Single Event Effects (SEEs) can have a significant impact on the performance and reliability of the system. This work is dedicated to investigating the reliability of systems based on programmable hardware and Real-time operating Systems (RTOS) in the presence of architectural faults induced by soft errors in the configuration memory of the programmable hardware. We performed a proton radiation test campaigned at PSI radiation facility to identify the fault model affecting the configuration memory of Xilinx Zynq-7020 reconfigurable AP-Soc Device. The identified fault model in terms of SEU and MBU clusters has been used to evaluate the impact of proton-induced faults on applications running within FreeRTOS on a Microblaze soft processor. A Single Event Multiple Upset fault model resulting from a proton test is presented, focusing on characteristics such as shape, size, and frequency of observed cluster of errors. We conduct two fault injection campaigns and analyze the results to assess the effect of cluster size on system reliability. Moreover, we discuss software exceptions caused by faults that can affect the hardware structure of the soft processor.

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“…Most of them are designed for the verification of radio frequency systems (vii) Electrical Fault Generator. This is also called FIU (Fault Insertion Unit) [17] or FIBO (Fault Insertion Break-Out) [18]. This is an optional module required only for the testing of some UUTs, which allows simulating defects in the wiring such as open circuits (cut wires), ground connections, power connections, and pin-to-pin connections (a short circuit between wires)…”

mentioning

confidence: 99%

A Research Study for the Design of a Portable and Configurable Ground Test System for the A400M Aircraft

Larios

Barbancho

Biscarri

et al. 2019

International Journal of Aerospace Engineering

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This paper presents a study of the most suitable ground test equipment for the Airbus A400M aircraft aimed at optimizing a design that combines portability, flexibility, and configurability. The study is based on current trends in the configuration of the different parts that are involved in the process of designing Aircraft Interface Modules (AIMs). Researches have been conducted facing the real problems of data acquisition and control in the assembly, maintenance, and repair processes of aircraft. In this sense, the number of signals used simultaneously in historical tests has been determined to be a parameter that plays an important role in the analysis. This work is within the framework of a project that our working group of the Department of Electronic Technology has carried out together with the company Airbus Defense and Space (Airbus DS). Thus, all the analyses and researches for the different configurations of the test equipment have been validated for the company. Some state-of-the-art systems have been considered in the process of designing the structure of the test system while analyzing the main advantages and drawbacks. Every hardware or software component was identified and justified according to its importance with respect to the use case. A comparison of how every approach meets the requirements was taken into account to define a methodology for designing a portable and configurable ground testing system. Thus, the conclusions of our study are being used by Airbus DS for the design of a prototype for the next generation of AIMs in A400M.

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SEFI cross-section evaluation by fault injection software approach and hardware detection

Cited by 6 publications

References 12 publications

Multiscale, Multiphysics Modeling and Simulation of Single-Event Effects in Digital Electronics: From Particles to Systems

Multiscale, Multiphysics Modeling and Simulation of Single-Event Effects in Digital Electronics: From Particles to Systems

Exploring the Impact of Soft Errors on the Reliability of Real-Time Embedded Operating Systems

A Research Study for the Design of a Portable and Configurable Ground Test System for the A400M Aircraft

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