2007
DOI: 10.1021/nl0710248
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Selective Plating for Junction Delineation in Silicon Nanowires

Abstract: The in situ growth of p-n junctions in silicon nanowires enables the fabrication of a variety of nanoscale electronic devices. We have developed a method for selective coating of Au onto n-type segments of silicon nanowire p-n junctions. Selective plating allows for quick verification of the position of p-n junctions along the nanowire using electron microscopy and allows for measurement of segment length.

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Cited by 6 publications
(9 citation statements)
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“…This allowed the integration of two independent electrical contacts on each n + segment to estimate the source/drain series resistance of the device. Moreover, the 1-μm-long p − body minimized the impact of short-channel effects in determining the effective mobility of the SiNW MOSFETs; doped segments as short as 120 nm have been demonstrated under these conditions . Following VLS growth, the Au catalyst particles were removed by selective wet etching, and the SiNWs were thermally oxidized using dry O 2 in an isothermal furnace held at 700 °C for 4 h .…”
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confidence: 99%
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“…This allowed the integration of two independent electrical contacts on each n + segment to estimate the source/drain series resistance of the device. Moreover, the 1-μm-long p − body minimized the impact of short-channel effects in determining the effective mobility of the SiNW MOSFETs; doped segments as short as 120 nm have been demonstrated under these conditions . Following VLS growth, the Au catalyst particles were removed by selective wet etching, and the SiNWs were thermally oxidized using dry O 2 in an isothermal furnace held at 700 °C for 4 h .…”
mentioning
confidence: 99%
“…Transmission electron microscopy (TEM) was used to study the structural properties of as-grown and thermally oxidized n + −p − −n + SiNWs. Selective electroless plating of Au metal on the n + relative to the p − SiNW segments was used to determine the segment lengths relative to the Au catalyst particle . Figure a−d shows the schematic and plan-view TEM images of a representative as-grown SiNW (not plated) collected near the base of the first n + segment, the midpoint of the p − segment, and the tip of the second n + segment using the Au tip as a measurement reference.…”
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“…Group IV semiconductor nanowires (NWs) are predominant nanostructures that are anticipated for use in next-generation transistor channels, solar cells, sensors, and so forth. They have been extensively investigated in the past decades. The control of doping impurities is essential for control of carrier behavior in the aforementioned devices. , There have been myriad studies focusing on the impurity doping effect in Group IV semiconductor NWs. There are three kinds of doping, ex situ doping, in situ doping, and surface doping. Among the doping methods, ion implantation technique, which is one of the ex situ doping methods, is the most well-known method.…”
Section: Introductionmentioning
confidence: 99%