Selective Runtime Memory Disambiguation in a Dynamic Binary Translator

Guo, Bolei; Wu, Youfeng; Wang, Cheng; Bridges, Matthew J.; Ottoni, Guilherme; Vachharajani, Neil; Chang, Jonathan; August, David I.

doi:10.1007/11688839_6

Cited by 11 publications

(15 citation statements)

References 12 publications

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“…Extensive use of pointers and pointer arithmetic in these applications complicate memory disambiguation and dependence testing. Even though research shows that a pair of memory accesses rarely alias until and unless aliasing is obvious [11], compilers generate conservative code to ensure correctness which limits vectorization opportunities [22]. For example, Figure 1a shows As stated before, a recent approach to vectorization, SLP [14], performs vectorization at basic block level.…”

Section: Motivationmentioning

confidence: 99%

Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment

Kumar

Martínez

González

2013

20th Annual International Conference on High Performance Computing

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Abstract-Compiler based static vectorization is used widely to extract data level parallelism from computation intensive applications. Static vectorization is very effective in vectorizing traditional array based applications. However, compilers inability to reorder ambiguous memory references severely limits vectorization opportunities, especially in pointer rich applications. HW/SW co-designed processors provide an excellent opportunity to optimize the applications at runtime. The availability of dynamic application behavior at runtime will help in capturing vectorization opportunities generally missed by the compilers. This paper proposes to complement the static vectorization with a speculative dynamic vectorizer in a HW/SW co-design processor. We present a speculative dynamic vectorization algorithm that speculatively reorders ambiguous memory references to uncover vectorization opportunities. The hardware checks for any memory dependence violation due to speculative vectorization and takes corrective action in case of violation. Our experiments show that the combined (static + dynamic) vectorization approach provides 2x performance benefit compared to the static vectorization alone, for SPECFP2006. Moreover, dynamic vectorization scheme is as effective in vectorization of pointer-based applications as for the array-based ones, whereas compilers lose significant vectorization opportunities in pointer-based applications.

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Section: Motivationmentioning

confidence: 99%

Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment

Kumar

Martínez

González

2013

20th Annual International Conference on High Performance Computing

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“…Thus, most existing software dynamic translation (SDT) systems, such as Dynamo [14], DynamoRio [15], Transmeta [26], and Daisy [27], only perform alias analysis in the form of instruction inspection, which disambiguates two memory references if they access either different memory regions or their addresses have the same base register and different offsets. As has been demonstrated by prior research [28], instruction inspection can only disambiguate one-third of all memory references in SPEC CUP2000 integer benchmarks, greatly restricting aggressive code transformations.…”

Section: Trace Optimization and Parallelizationmentioning

confidence: 96%

“…However, because symbolic evaluation performs path-sensitive program analysis and data-flow information is based on symbolic values instead of lexical names, it performs more precise program analysis than traditional data-flow analysis [29]. For memory disambiguation, we follow the idea of [28] and divide all memory references into groups with different base registers. If the ranges of addresses covered by two groups are disjoint, memory references in one group are guaranteed not to alias with those in the other group.…”

Section: Research Overviewmentioning

confidence: 99%

“…Memory disambiguation is a standard technique employed by many parallelization and OoO execution systems to execute memory reference instructions (i.e., loads and stores) out of program order. Both software-based and hardware-based techniques have been developed, and experimental results have shown approximately 80% accuracy in memory disambiguation for some applications [28,95].…”

Section: Go Back Tomentioning

confidence: 99%

“…However, because symbolic evaluation performs path-sensitive program analysis and dataflow information is based on symbolic values instead of lexical names, it performs more precise program analysis than traditional data-flow analysis [29]. While symbolic evaluation has also been adpoted by prior research [28] to perform pointer analysis on hyberblocks, we extend it to perform general optimizations on atomic traces.…”

Section: Symbolic Executionmentioning

confidence: 99%

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Yang¹

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With the number of cores increasing rapidly but the performance per core increasing slowly at best, software must be parallelized in order to improve performance. Manual parallelization is often prohibitively time-consuming and error-prone (especially due to data races and memory-consistency complexities), and some portions of code may simply be too difficult to understand or refactor for parallelization. Most existing automatic parallelization techniques are performed statically at compile time and require source code to be analyzed, leaving a large fraction of software behind.In many cases, some or all of the source code and development tool chain is lost or, in the case of third-party software, was never available. Furthermore, modern applications are assembled and defined at run time, making use of shared libraries, virtual functions, plugins, dynamically-generated code, and other dynamic mechanisms, as well as multiple languages. All these aspects of separate compilation prevent the compiler from obtaining a holistic view of the program, leading to the risk of incompatible parallelization techniques, subtle data races, and resource over-subscription. All the above considerations motivate dynamic binary parallelization (DBP).This dissertation explores the novel idea of trace-based DBP, which provides a large instruction window without introducing spurious dependencies. We hypothesize that traces provide a generally good trade-off between code visibility and analysis accuracy for a wide variety of applications so as to achieve better parallel performance. Compared to the raw dynamic instruction stream (DIS), traces expose more distant parallelism opportunities because their average length is typically much larger than the size of the hardware instruction window. Compared to the complete control flow graph (CFG), traces only contain control and data dependencies on the execution path which is actually taken. More importantly, while DIS-based DBP typically only exploits fine-grained parallelism and CFG-based DBP typically only exploits coarse-grained parallelism, traces can be used as a unified representation of program execution to seamlessly incorporate the exploitation of both coarse-and fine-grained parallelism.We develop Tracy, an innovative DBP framework which monitors a program at run time and i Abstract ii dynamically identifies hot traces, parallelizes them, and caches them for later use so that the program can run in parallel every time a hot trace repeats. Our experimental results have demonstrated that for floating point benchmarks, Tracy can achieve an average speedup of 2.16x, 1.51x better than the speedup achieved by Core Fusion, one representative of DIS-based DBP techniques. Although the average speedup achieved by Tracy is only 1.04x better than the speedup achieved by CFG-based DBP, Tracy can speed up all floating point benchmarks while CFG-based DBP fails to parallelize three out of eight applications at all. The performance of Tracy is not always better than the performance of exist...

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Acceldroid: Co-designed acceleration of Android bytecode

Wang

Cintra

2013

Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

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A hardware/software co-designed processor transparently supports a ubiquitous ISA (e.g. x86) with diversified and innovative microarchitectural implementations.It leverages co-designed HW features and dynamic binary translation (DBT) SW to morph existing binary programs to scale performance and save power. On such systems, the portable bytecode of modern dynamic languages (e.g. Java, JavaScript, etc.) is first translated into the code in the architecture ISA by the just-in-time (JIT) compilation in the bytecode virtual machine, and then into the code in the internal implementation ISA by the DBT. This not only incurs the translation overheads twice, but also brings significant emulation inefficiency as the DBT does not have the high level bytecode information. In this paper, we present AccelDroid, which accelerates the Android Dalvik bytecode execution on the HW/SW co-designed processor through direct bytecode translation in the DBT. Our experiments on a HW/SW co-designed Transmeta Efficeon machine show that AccelDroid can improve performance by 78% and save energy by 40% for the CaffeineMark 3.0 benchmark suite. OverheadsCustomized HW/SW Co-Design

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Selective Runtime Memory Disambiguation in a Dynamic Binary Translator

Cited by 11 publications

References 12 publications

Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment

Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment

Trace-Based Dynamic Binary Parallelization

Acceldroid: Co-designed acceleration of Android bytecode

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