Selective Si and SiGe epitaxial heterostructures grown using an industrial low-pressure chemical vapor deposition module

Abstract

Low-temperature epitaxial growth of Si and Si1−xGex (referred to as SiGe, hereafter) has been obtained using an industrial, 200 mm, single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content ⩽30% have been studied for buried channel applications in (PMOSFET) devices or as base for heterojunction bipolar transistors (HBTs). The dependence of Si and SiGe deposition rates on filling ratio and exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. In contrast to selective Si growth where the global loading effect decreases slowly with temperature, the growth rate of SiGe at low temperature is strongly dependent on the oxide coverage. The addition of HCl into the gas mixture allows minimizing the dependence of the SiGe growth rate on both oxide coverage and window size. The effect of the addition of HCl on Ge and dopants incorporation is investigated on bare and/or device wafers. Results on facet formation and orientations are also presented for selective Si and SiGe growths. Finally, we report basic electrical results on selective Si epitaxial and SiGe heteroepitaxial structures, which have been integrated in PMOSFET and HBT devices.

Selective epitaxial growth of stepwise SiGe:B at the recessed sources and drains: A growth kinetics and strain distribution study

“…Reduced global and micro-loading effects were reported when the process pressure was low, such as in UHV-CVD. 25,26 However, other factors such as chemical and thermal effects led to growth rate differences between the bulk and patterned wafers. [27][28][29] The cross-sectional TEM images after selected process cycles are shown in Fig.…”

Selective epitaxy growth of Si1−xGex layers for MOSFETs and FinFETs

“…4 have to be minimized. The importance to establish an epi-model for SEG is highlighted when the growth faces pattern dependency in which the SiGe layer profile is affected by the pattern layout [15,17,21,38,[40][41][42][43][44]. During recent years, various methods have been proposed to decrease the pattern dependency in SEG of SiGe layers but an effective method which completely eliminates this problem has not yet been presented [15,17].…”

“…The reason for pattern dependency relates to the gas kinetics and non-linear gas consumption over the patterned wafer [17,37,38]. The kinetics of CVD growth can physically be described by classical boundary layer theory assuming a laminar gas flow over the wafer [45].…”

Comprehensive Evaluation and Study of Pattern Dependency Behavior in Selective Epitaxial Growth of B-Doped SiGe Layers

“…SEG of SiGe layers is usually performed on wafers containing chips with various size openings. The pattern dependency of deposition leads to variations in Ge content and growth rate across the chip and across the wafer, and this profile variation leads to variations in device performance [5]- [10]. Nonuniformity of epideposition will also cause differences from wafer to wafer as chip design or the architecture (oxide or nitride with a specific thickness) changes.…”

“…Nonuniformity of epideposition will also cause differences from wafer to wafer as chip design or the architecture (oxide or nitride with a specific thickness) changes. Many studies have explored methods to improve layer profile uniformity over a wafer [5], [6], [9], [10]. Some of these reports show that the pattern dependency can be decreased (<5%) [9] but so far there is no remedy to totally eliminate the pattern dependency problem.…”