Selective State Retention Power Gating Based on Gate-Level Analysis

Greenberg, Shlomo; Rabinowicz, Joseph; Tsechanski, Ron; Paperno, E.

doi:10.1109/tcsi.2013.2286029

Cited by 8 publications

(11 citation statements)

References 10 publications

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“…However, this method requires a formal representation of the entire design, which is not always available, and also no automated techniques are proposed. The two recently published SSRPG approaches introduced by [16,17] provide pure formal methods for automatic selecting of all the FF's, which require retention and are essential for a proper system recovery upon power-up. Experimental results show a significant reduction of about 80% of the retention cells area overhead.…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, minimizing the number of retention FFs not only results in reducing the area overhead but also reduces the additional wiring required in SRPG. Although it is shown in [16] that a significant potential area reduction of about 9% of the chip area can be achieved, the added wiring required in SRPG is ignored. In SSRPG, the retention cells footprint can be simply deducted from the total cell area, but the wire-length deduction is not straightforward since it can only be obtained after completing the physical design flow.…”

Section: Introductionmentioning

confidence: 99%

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A New Physical Design Flow for a Selective State Retention Based Approach

Rabinowicz

Greenberg

2021

JLPEA

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This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design. Power Gating (PG) techniques were first developed to mitigate these leakage currents, but they result in longer SoC wake-up periods due to loss of state. The common State Retention Power Gating (SRPG) approach was developed to overcome the PG technique’s loss of state drawback. However, SRPG resulted in a costly expense of die area overhead due to the additional state retention logic required to keep the design state when power is gated. Moreover, the physical design implementation of SRPG presents additional wiring due to the extra power supply network and power-gating controls for the state retention logic. This results in increased implementation complexity for the physical design tools, and therefore increases runtime and limits the ability to handle large designs. Recently published works on Selective State Retention Power Gating (SSRPG) techniques allow reducing the total amount of retention logic and their leakage currents. Although the SSRPG approach mitigates the overhead area and power limitations of the conventional SRPG technique, still both SRPG and SSRPG approaches require a similar extra power grid network for the retention cells, and the effect of the selective approach on the complexity of the physical design has not been yet investigated. Therefore, this paper introduces further analysis of the physical design flow for the SSRPG design, which is required for optimal cell placement and power grid allocation. This significantly increases the potential routing area, which directly improves the convergence time of the Place and Route tools.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A New Physical Design Flow for a Selective State Retention Based Approach

Rabinowicz

Greenberg

2021

JLPEA

Self Cite

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“…Probably great benefits can be obtained by minimizing expected energy consumption at the system level. For example, we have found that it is possible to design the architecture with the possibility of involving elements responsible for power gating [20][21][22] of individual elements, or the clock gating [23][24][25]. Also, while reviewing methods to reduce energy consumption, the method of local voltage reduction was considered.…”

Section: Introductionmentioning

confidence: 99%

Low Power QC-LDPC Decoder Based on Token Ring Architecture

2020

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The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimization. Then the clock gating of the decoder building blocks allows for a significant reduction in energy consumption without deterioration in other parameters of the decoder, particularly its error correction performance. We also provide experimental results for decoder implementations with different QC-LDPC codes, indicating important characteristics of the code parity check matrix, for which an energy-saving QC-LDPC decoder with the proposed architecture can be designed. The experiments are based on implementations in the Intel Cyclone V FPGA device. Finally, the presented architecture is compared with the other solutions from the literature.

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“…Greenberg et al recently proposed methods [9,10] for automatically classifying all the flip-flops (FFs) of a given design into two categories: essential FF (e-FF) and redundant FF (r-FF). [10] performs the analysis according to read/write criteria on the synthesized gate-level netlist with Binary Decision Diagram (BDD) as the data structure, while [9] represented the criteria as a set of formal properties using propositional formulas and then uses common formal verification tools to drive the identification of the e-FFs. Even though the proposed approaches are formally sound, they are difficult to be applied by nonformal experts due to the required effort to provide proper input constraints using BDDs.…”

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confidence: 99%

“…In addition, They need massive parallel processing to achieve reasonable runtime, leaving scalability a major concern. Compared with [9,10], our proposed method verifies power intention and retention scheme in the early phase of design flow by symbolic simulation [4,5], which allows us to handle not only gate-level but also RTL designs without logic synthesis. Performing the analysis at the RTL instead of gate-level makes it easier for the designer to inspect the results.…”

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confidence: 99%

Scalable sequence-constrained retention register minimization in power gating design

Chiang

Chang

Liu

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Retention registers are utilized in power gating design to hold design state during power down and to allow safe and fast system reactivation. Since a retention register consumes more power and costs more area than a non-retention register, it is desirable to minimize the use of retention registers. However, relaxing retention requirement to a minimal subset of registers can be computationally challenging. In this paper, we adopt satisfiability solving for scalable selection of registers whose retention is unnecessary and exploit input sequence constraints to increase the number of non-retention registers. Empirical results on industrial benchmarks show that our proposed methods are efficient and effective in identifying non-retention registers.

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Selective State Retention Power Gating Based on Gate-Level Analysis

Cited by 8 publications

References 10 publications

A New Physical Design Flow for a Selective State Retention Based Approach

A New Physical Design Flow for a Selective State Retention Based Approach

Low Power QC-LDPC Decoder Based on Token Ring Architecture

Scalable sequence-constrained retention register minimization in power gating design

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