Self-align implantation for
            <i>n</i>
            <sup>+</sup>
            -layer technology (SAINT) for high-speed GaAs ICs

Yamasaki, K.; Asai, K.; Mizutani, Tomoko; Kurumada, K.

doi:10.1049/el:19820080

Cited by 70 publications

(8 citation statements)

References 1 publication

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“…1) has the following advan tages over less complicated shapes of one , two , or three layer dielectric dummy gates [13][14][15][16][17]: first, the wide base of the lower layer 1 provides the mechanical strength of the dummy gate and its adhesion to the substrate. Second, a combination of wide (2) and nar row (3) parts of the dummy gate, involving the second and the third dielectric layers, makes the profile nega tive, which is essential to obtaining a high quality sub micron metal gate electrode by lift off lithography, with a narrow part 3 determining the gate length.…”

Section: Resultsmentioning

confidence: 99%

“…The devised technology for submicron gate fabrica tion using a four layer dielectric dummy gate was imple mented in the process flow of self aligned MESFETs [16] and MICs based on them [17]. The characteristics of MESFETs produced by this technology are listed in Table 2.…”

Section: Planarization and Rie Of Photoresist And Formation Of A Submmentioning

confidence: 99%

“…One of the cutting edge tech niques enabling one to obtain MESFETs with high per formance is the technique of self aligned device ele ments, particularly, self aligned gate and source and drain contact regions of the transistor [5][6][7][8][9][10][11][12][13][14][15][16][17]. The dis tinctive features of this method are the fact that the res olution of the lithography under use is much higher than the obtained gate length, and that the constitutive operations are performed in the following sequence: Formation of a large sized self aligned element.…”

Section: Introductionmentioning

confidence: 99%

“…In the first one, a gate based on refractory metallization acts as a self alignment element, which can withstand activation high temperature annealing of an ion implanted layer (IIL) at T ≥ 850°С [5][6][7][8][9]. In the second group, a one , two , or three layer dielectric dummy gate is used as a self aligned element, which, on IIL high temperature annealing and diminishing dummy date length, is replaced by a metal gate [9][10][11][12][13][14][15][16][17]. The drawback of the first type of technologies is the significant resistivity of the refractory gate metallization, leading to the degra dation of MESFET frequency characteristics.…”

Section: Introductionmentioning

confidence: 99%

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Formation of a submicron GaAs MESFET gate using a four-layer dielectric dummy gate

et al. 2012

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In the present study, a technology for the formation of a submicron GaAs MESFET gate of 0.5-0.1 µm in length and above 0.5 µm in height using a four layer dielectric dummy gate was developed. Tech niques of chemical and plasma chemical deposition from a gaseous phase, differing in etch rates in a buffer solution of hydrofluoric acid, were used to prepare silicon oxide films. Different constructions of a multilayer structure with varying sequences of layers and thicknesses were studied. The conditions of chemical and plasma chemical etching of dielectrics allowing a dummy double T gate to be formed were determined. The employment of a sophisticatedly shaped dummy gate made it possible to obtain a gate electrode of a large cross section with a low length. The possibility in principle to fabricate a MESFET gate with a length of up to Lg = 0.1 µm using lithographic procedures with a minimal resolution of 1.0 µm was demonstrated.

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Section: Resultsmentioning

confidence: 99%

Section: Planarization and Rie Of Photoresist And Formation Of A Submmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Formation of a submicron GaAs MESFET gate using a four-layer dielectric dummy gate

et al. 2012

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“…Self-aligned planar gate technologies have been developed for this problem [7], [8]. These technologies have been widely used for digital and analog IC's because of the excellent uniformity and reproducibility of the device characteristics.…”

Section: Device Structurementioning

confidence: 99%

Enhancement-mode GaAs MESFET technology for low consumption power and low noise applications

Nakajima

Matsuzaki

Otobe

et al. 1994

IEEE Trans. Microwave Theory Techn.

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Ion-implanted enhancement-mode GqAs MESFET's with an advanced Lightly Doped Drain (LDD) structure have been developed for low cost, low consumption power, and low noise applications. The advanced LDD structure, which consists of step graded (n+, n', n') sourcddrain implanted regions and surrounding players located within the n+-layers, is effective to suppress the short channel effects and reduce sourcddrain parasitic resistance without increasing the parasitic capacitance. A manufacturable self-aligned process based on a dummy gate has also been developed for the fabrication of this structure. The 0.3 pm devices show a noise figure of less than 1 dB with an associated gain of higher than 9 dB at 6 GHz, even at 1 mW operation. Furthermore, standard deviations of noise figure and associated gain are as small as 0.05 dB (at an average of 0.83 dB) and 0.32 dB (at an average of 8.82 dB), respectively, under a 1 mW operation over a 3"@ wafer.

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GaAs broadband monolithic switches

Yamao

Sugeta

1986

Electron Comm Jpn Pt II

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A high‐frequency switch utilizing a GaAs FET as an analog switch is expected to operate in a broad band and can be integrated in a monolithic IC form. Since only a single power supply is needed for the gate bias and the power consumption of the switch can be made zero, it is useful in the area where a small size and low power consumption are required. To investigate the feasibility of a broadband GaAs monolithic switch, this paper first derives an equivalent circuit of the switch from the structural model of the FET and the relation between the switch characteristics and the device parameters of the FET. The design method of the switch is then developed. Next, the monolithic switches of SPDT and DPDT structures are fabricated by ion‐implantation technology and their characteristics are evaluated so that the validity of the equivalent circuit model is confirmed. The GaAs monolithic SPDT switch realized has the passband of dc to 3.3 GHz, insertion loss less than 0.7 dB (dc to 2 GHz), isolation more than 20 dB, switching time 2 ns and the maximum distortionless signal input power 20 dBm. Similarly, good performance has been obtained for the DPDT switch.

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Self-align implantation for n ⁺ -layer technology (SAINT) for high-speed GaAs ICs

Cited by 70 publications

References 1 publication

Formation of a submicron GaAs MESFET gate using a four-layer dielectric dummy gate

Formation of a submicron GaAs MESFET gate using a four-layer dielectric dummy gate

Enhancement-mode GaAs MESFET technology for low consumption power and low noise applications

GaAs broadband monolithic switches

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Self-align implantation for n + -layer technology (SAINT) for high-speed GaAs ICs

Cited by 70 publications

References 1 publication

Formation of a submicron GaAs MESFET gate using a four-layer dielectric dummy gate

Formation of a submicron GaAs MESFET gate using a four-layer dielectric dummy gate

Enhancement-mode GaAs MESFET technology for low consumption power and low noise applications

GaAs broadband monolithic switches

Contact Info

Product

Resources

About

Self-align implantation for n ⁺ -layer technology (SAINT) for high-speed GaAs ICs