Self-aligned blocking integration demonstration for critical sub-30-nm pitch Mx level patterning with EUV self-aligned double patterning

Raley, Angélique; Lee, Joe; Smith, Jeffrey; Sun, Xingsheng; Farrell, Richard A.; Shearer, Jeffrey C.; Xu, Yuheng; Ko, Akiteru; Metz, Andrew; Biolsi, Peter; Devilliers, Anton; Arnold, John; Felix, Nelson

doi:10.1117/1.jmm.18.1.011002

Cited by 6 publications

(5 citation statements)

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“…Deep UV photolithography using 193 nm light is highly reliable and economically robust, even at sub-10 nm feature nodes. Achieving these feature sizes in manufacturing relies on litho etch litho etch (LELE) multipatterning, where more than one exposure step is used in a single patterning layer to produce features with size and pitch that are much smaller than those imaged by a single mask. , In contrast, “bottom-up” or “additive” processes work to deposit or create material only in regions where it is needed, avoiding the need for material removal. Aspects of bottom-up processing are employed in several alternatives to lithography, including nanoimprinting or embossing, scanning probes, direct printing, electrostatic self-assembly, directed self-assembly (DSA) of block copolymers, and chemical assembly of organic electronics. − “Bottom-up” methods can significantly reduce material waste and energy consumption, so they remain an important direction for research exploration.…”

Section: Introductionmentioning

confidence: 99%

Area-Selective Deposition: Fundamentals, Applications, and Future Outlook

Parsons

Clark²

2020

Chem. Mater.

238

276

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This review provides an overview of area-selective thin film deposition (ASD) with a primary focus on vapor-phase thin film formation via chemical vapor deposition (CVD) and atomic layer deposition (ALD). Areaselective deposition has been successfully implemented in microelectronic processes, but most approaches to date rely on high-temperature reactions to achieve the desired substrate sensitivity. Continued size and performance scaling of microelectronics, as well as new materials, patterning methods, and device fabrication schemes are seeking solutions for new low-temperature (<400 °C) ASD methods for dielectrics, metals, and organic thin films. To provide an overview of the ASD field, this article critically reviews key challenges that must be overcome for ASD to be successful in microelectronics and other fields, including descriptions of current process application needs. We provide an overview of basic mechanisms in film nucleation during CVD and ALD and summarize current known ASD approaches for semiconductors, metals, dielectrics, and organic materials. For a few key materials, selectivity is quantitatively compared for different reaction precursors, giving important insight into needs for favorable reactant and reaction design. We summarize current limitations of ASD and future opportunities that could be achieved using advanced bottom-up atomic scale processes.

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Section: Introductionmentioning

confidence: 99%

Area-Selective Deposition: Fundamentals, Applications, and Future Outlook

Parsons

Clark²

2020

Chem. Mater.

238

276

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“…The results of this work identified the advantages of each integration flow from an RC and via resistance point of view. The model also included secondary effects of BEOL patterning such as line edge roughness (LER) 46 – 48 and considered the impact of EUV lithography and EUV + self-aligned double patterning (SADP) required to achieve sub-30 nm pitch. From these results, all three integration approaches were shown to be relatively equivalent.…”

Section: Logic Technologymentioning

confidence: 99%

Review of virtual wafer process modeling and metrology for advanced technology development

Hargrove

Wen

Yim

et al. 2023

J. Micro/Nanopattern. Mats. Metro.

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Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development is a major contributor to time and cost overruns. The growing inability to characterize many of the subtle and complicated features and yield limiting factors of a given technology is another serious constraint. We demonstrate the use of process modeling, virtual wafer fabrication, and virtual metrology in process development of advanced logic and memory. Accurate and predictive process modeling, in combination with virtual metrology enables the characterization of any feature on any given structure, is becoming a key requirement in advanced technology development. Virtual fabrication also accelerates the semiconductor development cycle, by substituting limited and lengthy wafer-based experiments with fast, large-scale virtual design of experiment. Several applications of virtual process modeling and metrology are illustrated in 3D NAND, DRAM, and logic technology. These applications include studies of 3D NAND pillar etch alignment (including tilt, twist, and bowing), DRAM capacitor process window optimization, advanced FinFET logic pitch-walking, and BEOL performance optimization.

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“…EUV with self-aligned double patterning (SADP) has also been considered, especially for the pitch scaling of critical interconnect layers. Double patterning achieves pitch halving in the final feature by using the spacer defined approach, and self-aligned block (SAB) mitigates the block placement error by leveraging etch selectivity and material filling capability [11]. For further pitch scaling, continuous improvement in litho-film-etch co-optimization is necessary.…”

Section: Euv and Patterningmentioning

confidence: 99%

Enabling process technologies for advanced logic devices beyond FinFET era

Yamamoto

2023

Advanced Etch Technology and Process Integration for Nanopatterning XII

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This invited talk describes the enabling process technologies for advanced logic devices beyond FinFET era. Gate-all-around (GAA) improves electrostatics over FinFET and enables continuous gate length scaling. Complementary FET (CFET), which is a structure of stacked transistors, is a next candidate architecture for the continuous cell height scaling enablement. Interconnect pitch scaling will also play crucial role for it and go with RC reduction knobs such as Cu damascene extension, post Cu and airgap. For better area usage and performance enhancement, backside power delivery network (PDN) is an attractive option. For these enablement, continuous process and tool advancement is necessary not only on film, etch, lithography and wet, but also on wafer bonding and thinning technologies. We will also review our recent progress in EUV related solutions including self-aligned patterning.

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Self-aligned blocking integration demonstration for critical sub-30-nm pitch Mx level patterning with EUV self-aligned double patterning

Cited by 6 publications

References 0 publications

Area-Selective Deposition: Fundamentals, Applications, and Future Outlook

Area-Selective Deposition: Fundamentals, Applications, and Future Outlook

Review of virtual wafer process modeling and metrology for advanced technology development

Enabling process technologies for advanced logic devices beyond FinFET era

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