Self-Aligned Crystallographic Multiplication of Nanoscale Silicon Wedges for High-Density Fabrication of 3D Nanodevices

Abstract

High-density arrays of silicon wedges bound by {111} planes on silicon (100) wafers have been created by combining convex corner lithography on a silicon dioxide hard mask with anisotropic, crystallographic etching in a repetitive, self-aligned multiplication procedure. A mean pitch of around 30 nm has been achieved, based on an initial pitch of ∼120 nm obtained through displacement Talbot lithography. The typical resolution of the convex corner lithography was reduced to the sub-10 nm range by employing an 8 nm silicon dioxide mask layer (measured on the {111} planes). Nanogaps of 6 nm and freestanding silicon dioxide flaps as thin as 1–2 nm can be obtained when etching the silicon at the exposed apices of the wedges. To enable the repetitive procedure, it was necessary to protect the concave corners between the wedges through “concave” corner lithography. The produced high-density arrays of wedges offer a promising template for the fabrication of large arrays of nanodevices in various domains with relevant details in the sub-10 nm range.

3d Self-Aligned Fabrication of Suspended Nanowires by Crystallographic Nanolithography

“…As this is close to the minimum thickness for this procedure, the 6 nm slit at the apex is the lower limit for this material system and procedure. The cavity width is 12 nm and was determined to be rather uniform at five positions across the wafer [6]: 12.0 ± 0.5 nm (±1 SD_N).…”

“…Initial wedges are formed from a line pattern in silicon nitride, used as a hard mask for anisotropic etching of the (100)-silicon substrate, followed by LOCOS and another anisotropic silicon etching step [7]. Cavities are formed by "convex corner lithography" combined with anisotropic etching [6]. Nanowires are then formed in the cavities through "irreversible processing", i.e.…”

“…Here we introduce an in-plane templating procedure with nm accuracy over the complete wafer for standard p-type silicon substrates, yielding nanowires in the 10 nm diameter range. More in detail, convex corner lithography [5,6], an emerging selfaligned nanopatterning technique, is employed to create nano-cavities at the apex of silicon wedges [6]. Essential steps have been added to this basic scheme to create a template for suspended nanowires of ∼100 nm length, and to create a strategy for controlled release etching.…”

“…Figure 1: Process flow for template cavity fabrication. Starting from the silicon wedge array (a), a low temperature thermal oxidation follows (b), then HF thinning of SiO2 (c) and finally TMAH etching of silicon (d).Adapted from[6] with permission.…”