Self-aligned double-patterning (SADP) friendly detailed routing

Mirsaeedi, Minoo; Torres, J. Andres; Anis, Mohab

doi:10.1117/12.877601

Cited by 30 publications

(25 citation statements)

References 8 publications

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“…Optimal decomposition is very difficult because of many variations of mandrel and trim patterns. 1 Mirsaeedi et al [13] tried grid routing for SID-type SADP but setting of mandrel and dummy mandrel patterns is complex and they did not show how to avoid coloring conflicts during routing process. Gao and Pan [14] proposed the first SID-type SADP-aware routing approach of handling 2-D patterns on multilayer designs.…”

mentioning

confidence: 99%

Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods

Kodama

Ichikawa

Nakayama

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Although self-aligned double and quadruple patterning (SADP, SAQP) have promising processes for sub-20 nm node advanced technologies and beyond, not all layouts are compatible with them. In advanced technologies, feasible wafer image should be generated effectively by utilizing SADP and SAQP where a wafer image is determined by a selected mandrel pattern. However, predicting a mandrel pattern is not easy since it is different from the wafer image (or target pattern). In this paper, we propose new routing methods for spacer-is-dielectric (SID)-type SADP, SID-type SAQP, and spacer-is-metal (SIM)-type SADP to generate a feasible layout satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SID-type SADP) or three colors (SID-type SAQP and SIM-type SADP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, we try to reduce hotspots (potentially defective regions) by the proposed dummy pattern flipping for SID-type SADP. In experiments, feasible layouts meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed.Index Terms-Design for manufacturing, lithography, routing, self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP).

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mentioning

confidence: 99%

Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods

Kodama

Ichikawa

Nakayama

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…To date, manufacturing-friendly detailed routing studies follow the paradigms of sequential routing [11], [13], [28], [37], [45], [46] and negotiation-congestion-based routing technique [8], [9]. When a router accesses an I/O pin locally, it creates a routing interval pattern on M2 for the net connection as shown in Fig.…”

Section: Pin Access Planningmentioning

confidence: 99%

“…Reference [45] presents the first SADP-aware detailed routing study by considering SADP-specific constraints during sequential routing procedure. Reference [13] further improves the routing results by incorporating coloring scheme and layer assignment into a sequential router.…”

Section: Manufacturing-friendly Unidirectional Routingmentioning

confidence: 99%

“…Most existing manufacturing-friendly studies focus on the coloring scheme of routing patterns while leveraging SAMP-specific manufacturing constraints [8], [9], [11], [13], [28], [37], [45], c 2017 Information Processing Society of Japan [46], [57], [68]. Reference [45] presents the first SADP-aware detailed routing study by considering SADP-specific constraints during sequential routing procedure.…”

Section: Manufacturing-friendly Unidirectional Routingmentioning

confidence: 99%

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Toward Unidirectional Routing Closure in Advanced Technology Nodes

Pan

2017

IPSJ Transactions on System LSI Design Methodology

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Abstract:In advanced technology nodes, unidirectional layout is strongly preferred for high-density metal layers for better manufacturability. The lithography printing of unidirectional layout can be tightly controlled with illumination source optimization and resolution enhancement techniques. Meanwhile, with the unidirectional layout, self-aligned double and quadruple patterning can be applied to achieve finer pitches beyond the resolutions limits of 193 nm lithography tools. However, unidirectional layout style introduces significant impacts on the physical design flow. Notably, unidirectional routing limits the standard cell pin accessibility, which makes manual cell layout design and optimization more and more challenging under modern standard cell architecture. In the routing phase, routing densities and resource competitions on lower metal layers are becoming increasingly high, where intelligent approaches are needed to resolve routing resource competitions for unidirectional routing closure. Moreover, post-routing optimization is inevitable to avoid significant engineering-changing-efforts for unidirectional routing under advanced manufacturing constraints. In this paper, we present a holistic approach, including standard pin access evaluation/optimization, pin access and routing co-optimization and post-routing optimization, to enable unidirectional routing closure in advanced technology nodes.

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“…To incorporate SADP constraints into early design stages, there are several studies [11]- [14] dealing with the SADPaware routing problem. However, to date, works studying how multiple patterning and decomposition impact SC I/O pin design are lacking, especially as pin congestion and routability become increasingly critical to the overall physical design results.…”

mentioning

confidence: 99%

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization

Cline

Yeric

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Self-aligned double patterning (SADP) is being considered for use at the 10-nm technology node and below for routing layers with pitches down to ∼50 nm because it has better line edge roughness and overlay control compared to other multiple patterning candidates. To date, most of the SADPrelated literature has focused on enabling SADP-legal routing in physical design tools while few attempts have been made to address the impact SADP routing has on local, standard cell (SC) I/O pin access. At the same time, via layers are used to connect the local SADP routing layers to the I/O pins on lower metal layers. Due to the high via density on the Via-1 layer, the litho-etch-litho-etch (LELE)-aware Via-1 design becomes a necessity to achieve legal pin access at the SC level. In this paper, we present the first study on SADP-aware pin access and layout optimization at the SC level. Accounting for SADP-specific and Via-1 design rules, we propose a coherent framework that uses depth first search, mixed integer linear programming, and backtracking method to enable LELE friendly Via-1 design and simultaneously optimize SADP-based local pin access and within-cell connections. Our experimental results show that, compared with the conventional approach, our framework effectively improves pin access of the SCs and maximizes the pin access flexibility for routing.Index Terms-Double patterning, pin access, self-aligned double patterning (SADP), standard cell (SC) layout, Via-1 assignment.

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Self-aligned double-patterning (SADP) friendly detailed routing

Cited by 30 publications

References 8 publications

Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods

Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods

Toward Unidirectional Routing Closure in Advanced Technology Nodes

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization

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