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Although self-aligned double and quadruple patterning (SADP, SAQP) have promising processes for sub-20 nm node advanced technologies and beyond, not all layouts are compatible with them. In advanced technologies, feasible wafer image should be generated effectively by utilizing SADP and SAQP where a wafer image is determined by a selected mandrel pattern. However, predicting a mandrel pattern is not easy since it is different from the wafer image (or target pattern). In this paper, we propose new routing methods for spacer-is-dielectric (SID)-type SADP, SID-type SAQP, and spacer-is-metal (SIM)-type SADP to generate a feasible layout satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SID-type SADP) or three colors (SID-type SAQP and SIM-type SADP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, we try to reduce hotspots (potentially defective regions) by the proposed dummy pattern flipping for SID-type SADP. In experiments, feasible layouts meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed.Index Terms-Design for manufacturing, lithography, routing, self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP).

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Although lithography conditions, such as NA, illumination condition, resolution enhancement technique (RET), and material stack on wafer, have been determined to obtain hotspot-free wafer images, hotspots are still often found on wafers. This is because the lithography conditions are optimized with a limited variety of patterns. For 40 nm technology node and beyond, it becomes a critical issue causing not only the delay of process development but also the opportunity loss of the business. One of the easiest ways to avoid unpredictable hotspots is to verify an enormous variety of patterns in advance. This, however, is time consuming and cost inefficient. This paper proposes a new method to create a group of patterns to cover pattern variations in a chip layout based on Higher-Order Local Autocorrelation (HLAC), which consists of two phases. The first one is the "analyzing phase" and the second is the "generating phase". In the analyzing phase, geometrical features are extracted from actual layouts using the HLAC technique. Those extracted features are statistically analyzed and define the "feature space". In the generating phase, a group of patterns representing actual layout features are generated by correlating the feature space and the process margin. By verifying the proposed generated patterns, the lithography conditions can be optimized efficiently and the number of hotspots dramatically reduced.