Self-aligned inversion-channel n-InGaAs, p-GaSb, and p-Ge MOSFETs with a common high κ gate dielectric using a CMOS compatible process

Fu, Chia-Ming; Lin, Yan-Ting; Lee, W.C.; Lin, T. D.; Chu, R. L.; Chu, L. K.; Chang, P.; Chen, M.H.; Hsueh, Wei Jen; Chen, Sike; Brown, Gail J.; Chyi, Jen Inn; Kwo, J.; Hong, M.

doi:10.1016/j.mee.2015.04.098

Cited by 16 publications

(3 citation statements)

References 32 publications

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“…Even the technology of high-dielectric constant (κ) oxide and metal gate, introduced since the 45-nm node, still utilizes a thin SiO 2 layer sandwiched between the Si channel and the high-κ dielectric . To overcome the fundamental limitation of carrier mobility in Si for enhancing MOSFET performances to the next level, Ge and GaAs (InGaAs), with higher carrier mobility than Si, have been considered as the new p - and n -channels. − To avoid the low-κ interfacial layer such as SiO 2 in aggressively scaling the effective oxide thickness, direct deposition of high-κ on Ge and GaAs (InGaAs) is also demanded. On passivation of GaAs (InGaAs) MOS, finding a directly deposited high-κ oxide that provides a low trap density is a technologically important and scientifically interesting challenge.…”

Section: Introductionmentioning

confidence: 99%

Ultrahigh Vacuum Annealing of Atomic-Layer-Deposited Y₂O₃/GaAs in Perfecting Heterostructural Chemical Bonding for Effective Passivation

Chen

Lin

et al. 2023

ACS Appl. Electron. Mater.

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Direct deposition of high-dielectric-constant oxides on high-mobility semiconductors with low trap densities is the key to high-performance metal−oxide−semiconductor (MOS) devices. Atomic layer deposition (ALD) has been employed in precise thin oxide depositions with relatively low temperatures in the semiconductor device fabrication industry. Herein, we compare the electronic structures of nanometer-thick ALD-Y 2 O 3 on freshly grown GaAs(001)−4 × 6 without and with ultrahigh vacuum (UHV) annealing to 600 °C. In situ X-ray photoelectron spectroscopy (XPS) and in situ synchrotron radiation photoelectron spectroscopy (SRPES) with the best surface sensitivity were utilized to study the samples, whose pristine conditions were preserved under UHV between the growth and the characterization. In the Y 2 O 3 film, the surface Y−OH bonding and the pure As atoms resulting from the ALD process were completely removed with UHV annealing. Additionally, no O deficiency was detected in the resolution limit of XPS, indicating the intactness of the O−Y bonding. The UHV annealing has reduced traps in the Y 2 O 3 film, leading to smaller frequency dispersions in the measured capacitance−voltage (C−V) curves of the MOS capacitors (MOSCAPs). At the same time, the enriched Ga−O−Y bonds effectively passivated the GaAs surface and strongly stabilized the Y 2 O 3 /GaAs interface, resulting in lower interfacial trap density (D it ) values from (2−3) × 10 12 eV −1 cm −2 to (0.7−2) × 10 12 eV −1 cm −2 and maintaining the high-temperature stability. We have elucidated the effects of UHV annealing on the interfacial chemistry and the thin oxide film of the ALD-Y 2 O 3 /GaAs(001)−4 × 6 in an atomic scale, and have correlated the electronic characteristics of the heterostructure with the electrical properties of the MOSCAPs.

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Section: Introductionmentioning

confidence: 99%

Ultrahigh Vacuum Annealing of Atomic-Layer-Deposited Y₂O₃/GaAs in Perfecting Heterostructural Chemical Bonding for Effective Passivation

Chen

Lin

et al. 2023

ACS Appl. Electron. Mater.

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“…To improve the performance of our transistors, I on and g m must be increased, for example, by the use of a self-aligned gate structure to avoid long ungated nanowire segments . Further, to decrease the subthreshold slope, the wire diameter should be reduced to improve electrostatics and the gate dielectric deposition optimized …”

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confidence: 99%

III–V Nanowire Complementary Metal–Oxide Semiconductor Transistors Monolithically Integrated on Si

et al. 2015

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Sweden 6 *These authors contributed equally 7 III−V semiconductors have attractive transport properties suitable for low-power, high-speed 8 complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to 9 co-integration of III−V n-and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on 10 low-cost Si substrates have so far hindered their use for large scale logic circuits. Using a novel 11 approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one 12 single growth step, we here demonstrate n-and p-type, III−V MOSFETs monolithically integrated on a 13Si substrate with high Ion/Ioff ratios using a dual channel, single gate-stack design processed 14 simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic 15 gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale 16 III−V MOSFET circuits on Si. 17 Keywords: III−V, CMOS, nanowire, inverter, NAND, InAs, GaSb, low-power logic, Si 18Geometric scaling has for decades been the main technology drive for integrated Si circuits whereas 19 materials integration plays an important role in the continued technology evolution. In future 20 generations, III−V semiconductors are considered candidates to replace Si as channel material in 21MOSFETs due to their high mobilities and injection velocities that will enable voltage scaling to 22 reduce the power consumption at maintained performance The vertical device geometry is attractive, since it allows for aggressive gate length scaling due to the 41 superior electrostatics of the gate-all-around geometry and a small device footprint enabling high 42 density circuits. In addition, Yakimets et al. have predicted power savings of 10-15% for a vertical 43 device layout as compared to a lateral geometry for the 7 nm technology node 20 . In this work we 44 have focused on InAs and GaSb as the channel materials based on their respective high electron and 45 hole mobilities suitable to achieve high performance of both n-and p-type MOSFETs 1 and 46 demonstrate the growth of both materials on Si substrates by metal-organic vapor phase epitaxy 47 (MOVPE) in a single growth step. The growth step reduces the need for complex processing 48 simplifying fabrication saving cost and time. Both n-and p-type MOSFETs exhibit high Ion/Ioff ratios 49 using the same gate stack, which is known to be a critical concern for III−V MOSFETs. which are substantial benefits as compared to growth approaches directly on Si 17, 22 . To achieve 56 selective growth of both types of nanowires, we exploit the fact that the chemical potential of 57 material dissolved in an Au particle during growth is increased with decreasing particle size due to 58 the higher surface-to-volume ratio. Eventually, the chemical potential approaches that of the gas 59 phase, reducing the driving force for material transport to the particles what is known as the Gibbs-60Thompson effect 23 . Since the solubil...

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“…[10][11][12] A "beyond Si" CMOS may consist of n-(In)GaAs and p-Ge (or p-GaSb) MOSFETs with a common gate dielectric and a CMOS compatible process, which requires high-temperature thermal stability and ALD-dielectrics. [13][14][15][16][17] The advantages of conformal coverage and the selflimiting nature in ALD have enabled its usage in depositing high-κ's in the semiconductor industry since the 45 nm node CMOS. Therefore, intensive research efforts of in-situ and ex-situ ALD-Al 2 O 3 and -HfO 2 on GaAs(001) have been taken to reduce D it s. [18][19][20][21][22][23] Surface treatments and interfacial passivation layers were employed prior to the ex-situ ALD, along with incorporating nitrogen at Al 2 O 3 =GaAs(001).…”

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confidence: 99%

Low interfacial trap density and high-temperature thermal stability in atomic layer deposited single crystal Y₂O₃/n-GaAs(001)

Lin

et al. 2016

Appl. Phys. Express

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A low interfacial trap density (D it) of 2.2 × 1011 eV−1 cm−2 has been achieved with an atomic layer deposited (ALD) single crystal Y2O3 epitaxially on n-GaAs(001), along with a small frequency dispersion of 10.3% (2.6%/decade) at the accumulation region in the capacitance–voltage (C–V) curves. The D it and frequency dispersion in the C–V curves in this work are the lowest among all of the reported ALD-oxides on n-type GaAs(001). The D it was measured using the conductance–voltage (G–V) and quasi-static C–V (QSCV) methods. Moreover, the heterostructure was thermally stable with rapid annealing at 900 °C under various durations in He and N2, which has not been achieved in the heterostructures of ALD-Al2O3 or HfO2 on GaAs.

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Self-aligned inversion-channel n-InGaAs, p-GaSb, and p-Ge MOSFETs with a common high κ gate dielectric using a CMOS compatible process

Cited by 16 publications

References 32 publications

Ultrahigh Vacuum Annealing of Atomic-Layer-Deposited Y₂O₃/GaAs in Perfecting Heterostructural Chemical Bonding for Effective Passivation

Ultrahigh Vacuum Annealing of Atomic-Layer-Deposited Y₂O₃/GaAs in Perfecting Heterostructural Chemical Bonding for Effective Passivation

III–V Nanowire Complementary Metal–Oxide Semiconductor Transistors Monolithically Integrated on Si

Low interfacial trap density and high-temperature thermal stability in atomic layer deposited single crystal Y₂O₃/n-GaAs(001)

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Self-aligned inversion-channel n-InGaAs, p-GaSb, and p-Ge MOSFETs with a common high κ gate dielectric using a CMOS compatible process

Cited by 16 publications

References 32 publications

Ultrahigh Vacuum Annealing of Atomic-Layer-Deposited Y2O3/GaAs in Perfecting Heterostructural Chemical Bonding for Effective Passivation

Ultrahigh Vacuum Annealing of Atomic-Layer-Deposited Y2O3/GaAs in Perfecting Heterostructural Chemical Bonding for Effective Passivation

III–V Nanowire Complementary Metal–Oxide Semiconductor Transistors Monolithically Integrated on Si

Low interfacial trap density and high-temperature thermal stability in atomic layer deposited single crystal Y2O3/n-GaAs(001)

Contact Info

Product

Resources

About

Ultrahigh Vacuum Annealing of Atomic-Layer-Deposited Y₂O₃/GaAs in Perfecting Heterostructural Chemical Bonding for Effective Passivation

Ultrahigh Vacuum Annealing of Atomic-Layer-Deposited Y₂O₃/GaAs in Perfecting Heterostructural Chemical Bonding for Effective Passivation

Low interfacial trap density and high-temperature thermal stability in atomic layer deposited single crystal Y₂O₃/n-GaAs(001)