III–V Nanowire Complementary Metal–Oxide Semiconductor Transistors Monolithically Integrated on Si

Abstract

Sweden 6 *These authors contributed equally 7 III−V semiconductors have attractive transport properties suitable for low-power, high-speed 8 complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to 9 co-integration of III−V n-and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on 10 low-cost Si substrates have so far hindered their use for large scale logic circuits. Using a novel 11 approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one 12 single growth step, we here demonstrate n-and p-type, III−V MOSFETs monolithically integrated on a 13Si substrate with high Ion/Ioff ratios using a dual channel, single gate-stack design processed 14 simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic 15 gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale 16 III−V MOSFET circuits on Si. 17 Keywords: III−V, CMOS, nanowire, inverter, NAND, InAs, GaSb, low-power logic, Si 18Geometric scaling has for decades been the main technology drive for integrated Si circuits whereas 19 materials integration plays an important role in the continued technology evolution. In future 20 generations, III−V semiconductors are considered candidates to replace Si as channel material in 21MOSFETs due to their high mobilities and injection velocities that will enable voltage scaling to 22 reduce the power consumption at maintained performance The vertical device geometry is attractive, since it allows for aggressive gate length scaling due to the 41 superior electrostatics of the gate-all-around geometry and a small device footprint enabling high 42 density circuits. In addition, Yakimets et al. have predicted power savings of 10-15% for a vertical 43 device layout as compared to a lateral geometry for the 7 nm technology node 20 . In this work we 44 have focused on InAs and GaSb as the channel materials based on their respective high electron and 45 hole mobilities suitable to achieve high performance of both n-and p-type MOSFETs 1 and 46 demonstrate the growth of both materials on Si substrates by metal-organic vapor phase epitaxy 47 (MOVPE) in a single growth step. The growth step reduces the need for complex processing 48 simplifying fabrication saving cost and time. Both n-and p-type MOSFETs exhibit high Ion/Ioff ratios 49 using the same gate stack, which is known to be a critical concern for III−V MOSFETs. which are substantial benefits as compared to growth approaches directly on Si 17, 22 . To achieve 56 selective growth of both types of nanowires, we exploit the fact that the chemical potential of 57 material dissolved in an Au particle during growth is increased with decreasing particle size due to 58 the higher surface-to-volume ratio. Eventually, the chemical potential approaches that of the gas 59 phase, reducing the driving force for material transport to the particles what is known as the Gibbs-60Thompson effect 23 . Since the solubil...

Impact of doping and diameter on the electrical properties of GaSb nanowires

“…Semiconductor nanowires (NWs) are promising building blocks for the next-generation nanoscale electronics due to their good electrostatics enabling aggressive gate length scaling. [1][2][3] The nanoscale geometry of NWs may provide strain accommodation through radial relaxation enabling high lattice-mismatch heteroepitaxy on, e.g., Si substrates with high crystal quality. 4 While the synthesis, processing, and applications of III-V materials have been studied for more than a decade, research on III-Sb NWs has attracted a growing interest only recently.…”

p-GaAs Nanowire Metal–Semiconductor Field-Effect Transistors with Near-Thermal Limit Gating

“…6,8 A key aspect in vertical array devices is that the gate-length is no longer constrained by lithography and instead controlled by layer thicknesses during processing, facilitating scaling to sub-100 nm gate length. This pathway has already been taken for p-GaSb, with the single horizontal nanowire devices of Dey et al 19 and Babadi et al 20 translated into vertical nanowire array structures by, e.g., Svensson et al 21 and…”

Near-thermal limit gating in heavily doped III-V semiconductor nanowires using polymer electrolytes

“…This is caused by several key challenges for p-type devices including lower intrinsic carrier mobility and difficulties in growth, doping and fabrication of high quality ohmic contacts and gates. Hence III-V nanowire CMOS typically features p-type transistors far less ideal than their n-type counterparts [5,10,11]. Here we present polymer electrolyte gated Be-doped p + -GaAs NWFETs with near-thermal limit gating that point out a path to filling this significant performance gap.…”