Researchers develop sutureless conductive patch with enhanced biostability and effect on heart conduction velocity.
The quality of interfaces and surfaces is crucial for the performance of nanoscale devices. A pertinent example is the close tie between current progress in gate-tunable and topological superconductivity using semiconductor/superconductor electronic devices and the hard proximity-induced superconducting gap obtained from epitaxial indium arsenide/aluminium heterostructures. Fabrication of devices requires selective etch processes; these only exist for InAs/Al hybrids, which precludes the use of other, potentially better material combinations in functional devices. We present a crystal growth platform based on three-dimensional structuring of growth substrates for synthesising semiconductor nanowires with in-situ patterned superconductor shells, which enables independent choice of material by eliminating etching. We realise and characterise all the most frequently used architectures in superconducting hybrid devices, finding increased yield and electrostatic stability compared to etched devices, along with evidence of ballistic superconductivity. In addition to aluminium, we present hybrid devices based on tantalum, niobium and vanadium.One dimensional semiconductor (SE) nanowires (NWs) proximity coupled to superconductors (SU) have attracted considerable attention from the condensed matter community since the prediction 1,2 and observation of Majorana zero-modes 3-5 , which have been proposed as a basis for topologically protected quantum information processors 6,7 . To ensure topological protection, methods for growing disorder-free 'hard-gap' SE/SU epitaxial hybrids were developed 8-10 . These materials utilise bottom-up crystal growth of InAs nanowires with uniform epitaxial aluminium coatings, an approach which has been extended to high mobility two-dimensional systems 11,12 and selective area grown networks 13,14 . The success of epitaxial InAs/Al hybrids lies in the ability to realise important device classes such as normal metal spectroscopic devices, 5,9,11,12 Josephson Junctions 15-18 for gate-controlled transmon qubits 19,20 , and superconducting Majorana islands 21-23 , using top-down processing to selectively remove the Al. A limitation of this method is that relying on post-process etching inherently limits materials choice. For instance, despite strong incentives to utilise technologically important superconductors such as Nb 24 and NbTiN 25 -which exhibit higher transition temperatures, critical magnetic fields and superconducting energy gaps -selectively removing Nb from InAs remains an unsolved problem. Similarly, InSb is an attractive semiconductor due to its high mobility, g-factor and strong spin-orbit coupling 25-28 . Yet, selectively removing even aluminum from InSb without damage is impossible with known methods. Thus, most potential improvements in epitaxial SE/SU technology are predicated on developing a materials-independent method for device fabrication. An attractive approach to eliminate etching is to employ an in-situ 'shadow approach' to mask specific segments along the NW from supe...
We report an electron-beam based method for the nanoscale patterning of the poly(ethylene oxide)/LiClO 4 polymer electrolyte. We use the patterned polymer electrolyte as a high capacitance gate dielectric in single nanowire transistors and obtain subthreshold swings comparable to conventional metal/oxide wrap-gated nanowire transistors. Patterning eliminates gate/contact overlap which reduces parasitic effects and enables multiple, independently controllable gates. The method's simplicity broadens the scope for using polymer electrolyte gating in studies of nanowires and other nanoscale devices.
We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favorable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
customersupport@researchsolutions.com
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.
Copyright © 2025 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.