InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments

Abstract

We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favorable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.

Catalyst shape engineering for anisotropic cross-sectioned nanowire growth

“…For the purpose of controlling and improving semiconducting nanowire (NW) devices for various applications1234567, an extensive research effort has been invested in studying NW growth; this was typically achieved by studying the different effects of user controlled parameters: (i) materials - including type and size of NW catalyst, the growth substrates and precursors, and (ii) by altering growth-system parameters, i.e., temperature and precursor flow891011121314151617. In the following report we present a new paradigm, that of catalyst shape engineering, as a useful tool to control NW growth results; in particular, we show that by imposing a non-hemispherical shape to the catalyst-substrate interface, anisotropic cross-sectioned NWs may be grown - NWs with potentially new physical characteristics.…”

Achieving short high-quality gate-all-around structures for horizontal nanowire field-effect transistors

“…Turning to horizontal wrap-gated nanowire transistors, these are of interest for basic research devices, e.g., quantum electronics, but also as a possible complement for vertical transistors in 3D-integrated circuits [21]. Fabrication of multiple independent wrap-gates has also been achieved in the horizontal orientation, giving a significant advantage on scalability over the vertical orientation [14].…”

“…A major limitation of horizontal wrap-gate nanowire transistors [13,14] is that the gate length is defined by wet-etching. This limits control and restricts the minimum achievable gate length [14].…”

“…A major limitation of horizontal wrap-gate nanowire transistors [13,14] is that the gate length is defined by wet-etching. This limits control and restricts the minimum achievable gate length [14]. Shorter gates are also intrinsically of lower quality in this instance because unintentional overetching introduces 'mouse-bite' defects-small holes in the gate metal and oxide that compromise both performance and yield [14].…”

Near-thermal limit gating in heavily doped III-V semiconductor nanowires using polymer electrolytes

“…This is useful because heavy doping provides a path to reduced contact and channel resistance. Additionally, PE gates are far simpler to produce than traditional metal-oxide wrap-gate structures [18][19][20][21] and utilise an intrinsically biocompatible material [22]. Nanopatterned PE gates have been used in applications from enacting external ionic doping of quantum devices [17,23] to ionic-to-electronic signal transduction [14].…”