p-GaAs Nanowire Metal–Semiconductor Field-Effect Transistors with Near-Thermal Limit Gating

Abstract

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical subthreshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio ∼10, on-resistance ∼700 kΩ, contact resistance ∼30 kΩ, peak transconductance 1.2 μS/μm, and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates while leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance.

Synthesis and Applications of III–V Nanowires

“…Finally, with respect to p-type NW MOSFET development, only relative success has been so far attained , despite the relatively high hole mobility of GaSb material. , The slow progress can be explained by the challenging antimonide epitaxial growth together with (1) the nonoptimum gate stack, (2) the relatively long gate lengths, (3) the challenge to obtain ohmic contacts with low contact resistance, , and (4) large diameters of GaSb NWs so far employed . Quite recently, an alternative p-type NW transistor has been proposed based on a GaAs NW MESFET …”

“…209 Quite recently, an alternative p-type NW transistor has been proposed based on a GaAs NW MESFET. 262 2.3.1.2. Nanowire Tunnel Field-Effect Transistors.…”

GaAs/AlGaAs Nanowire Array Solar Cell Grown on Si with Ultrahigh Power-per-Weight Ratio

“…Planar single axial p-i-n junction GaAs NW solar cell (NWSC) devices were fabricated utilizing EBL and a selective-area shell-etching process for both type I and type II GaAs NWs. In order to employ a controlled and homogeneous AlGaAs/GaAs shell etching from the single GaAs NW, a H 3 PO 4 /H 2 O 2 /H 2 O (1:1:200) wet etching recipe was used . For the type I single NWs, an asymmetric etching profile was created, where the AlGaAs/GaAs shell around the NW was etched for 2.5 min with an intentional overetching for 2 min carried out on the p-GaAs segment side additionally.…”

“…In order to employ a controlled and homogeneous AlGaAs/GaAs shell etching from the single GaAs NW, a H 3 PO 4 /H 2 O 2 /H 2 O (1:1:200) wet etching recipe was used. 54 For the type I single NWs, an asymmetric etching profile was created, where the AlGaAs/GaAs shell around the NW was etched for 2.5 min with an intentional overetching for 2 min carried out on the p-GaAs segment side additionally. In contrast to this, a symmetric etching for 1.5 min was employed to both the pand n-segment sides for the type II single NWs.…”

Schottky‐Contacted High‐Performance GaSb Nanowires Photodetectors Enabled by Lead‐Free All‐Inorganic Perovskites Decoration

“…Furthermore, the Schottky barrier between semiconductor and metal electrode can reduce the dark current of photodetectors. [18,[27][28][29] Beyond surface passivation, the construction of core-shell NWs and the introduction of stress, etc., [30][31][32][33][34] surface decoration is becoming a popular approach to control the surface Fermi level pinning effect of semiconductors' NWs. [35] With decoration, the carriers will transfer at the interfaces between NWs and decorated semiconductors, The surface Fermi level pinning effect promotes the formation of metalindependent Ohmic contacts for the high-speed GaSb nanowires (NWs) electronic devices, however, it limits next-generation optoelectronic devices.…”