Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

Hakim, M. A.; Tan, L.; Abuelgasim, A.; Mallik, Kanad; Connor, Samuel; Bousquet, A.; Groot, C. H. de; Redman-White, W.; Hall, S.; Ashburn, P.

doi:10.1109/ted.2010.2082293

Cited by 5 publications

(4 citation statements)

References 34 publications

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“…The peak transconductances (G M ) of H 2 annealed transistors were measured, and the values of 1.4 × 10 −3 and 1.1 × 10 −2 A/V were obtained for V DS = 0.05 and 1 V, respectively, which are noticeably better than those reported for planar MOSFETs with comparable 0.5/0.7-μm technology [8], [9] and also better than some aggressively scaled planar MOSFETs reported in [9] and [10]. This beneficial effect of the H 2 anneal could be integrated with our recently reported FILOX process for overlap capacitance reduction and silicidation process for S/D series resistance reduction [5] to deliver a significant benefit from VMOS devices for RF applications in mature lateral CMOS technologies.…”

Section: Discussionmentioning

confidence: 62%

“…S URROUND-GATE thick pillar vertical MOSFETs are being researched because they offer a high drive current per unit silicon area and can be easily integrated in a mature CMOS technology for low-cost RF transistors [1]- [5]. One of the challenges of vertical MOSFETs for this application is susceptibility to surface roughness and etch damage on the sidewalls of the silicon pillar.…”

Section: Introductionmentioning

confidence: 99%

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Improved Drive Current in RF Vertical MOSFETS Using Hydrogen Anneal

Hakim

Abuelgasim

Tan

et al. 2011

IEEE Electron Device Lett.

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Abstract-This letter reports a study on the effect of a hydrogen anneal after silicon pillar etch of surround-gate vertical MOSFETs intended for RF applications. A hydrogen anneal at 800• C is shown to give a 30% improvement in the drive current of 120-nm n-channel transistors compared with transistors without the hydrogen anneal. The value of drive current achieved is 250 μA/μm, which is a record for thick pillar vertical MOSFETs. This improved performance is obtained even though a sacrificial oxidation was performed prior to the hydrogen anneal to smooth the pillar sidewall. The values of subthreshold slope and DIBL are 79 mV/decade and 45 mV/V, respectively, which are significantly better than most values reported in the literature for comparable devices. The H 2 anneal is also shown to decrease the OFF-state leakage current by a factor of three.Index Terms-Fillet local oxidation (FILOX), hydrogen anneal, vertical MOSFET.

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Section: Discussionmentioning

confidence: 62%

Section: Introductionmentioning

confidence: 99%

Improved Drive Current in RF Vertical MOSFETS Using Hydrogen Anneal

Hakim

Abuelgasim

Tan

et al. 2011

IEEE Electron Device Lett.

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“…The main obstacle of shrinking the dimension of MOSFET is the decrease in gate controllability over the channel due to high electric field [1][2][3][4]. An alternative solution to improve the gate control over the channel is by adding an extra gate [5][6][7][8][9][10]. Multi-gate MOSFETs have been recognized promising candidates for future scaling of MOSFET technologies.…”

Section: Introductionmentioning

confidence: 99%

Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

Kaharudin¹,

Salehuddin²,

Zain³

et al. 2019

IJECE

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The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.

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“…Fully depleted configuration is an important feature used in most of double-gate and silicon-on-insulator (SOI) transistors [15][16][17][18][19][20]. The fully depleted channel is found to be very effective in mitigating the SCE [21][22][23]. The SCE become more prominent when the subthreshold swing (SS) is increased in which the degrading drain current (I D ) stands up against a gate voltage (V G ) and threshold roll-off to negative direction in the case of the n-channel transistor.…”

Section: Introductionmentioning

confidence: 99%

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

2019

IJRTE

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Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (L g ) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (L g ) does contributes a significant impact on the drain current (I D ), on-current (I ON ), off-current (I OFF ), I ON /I OFF ratio, subthreshold swing (SS) and transconductance (g m ). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both I ON and g m (max) are measured at 1680 µA/µm and 2.79 mS/µm respectively. Engineering (FKEKK), UTeM. Her research interest includes process and device simulation of nanoscale MOSFETs device, advanced CMOS design, optimization approach (DOE) and process parameter variability. Z. A. F. M. Napiah received the B.Eng. degree in electrical engineering and the M.Eng. degree in Microelectronic from Universiti Teknologi Malaysia (UTM). He received the Ph.D. degree in Microelectronics from Kanawa University, Japan. He is currently a senior lecturer at Faculty of Electronic and Computer Engineering (FKEKK), UTeM. His research interest includes process and device simulation of MOSFET device, advanced CMOS design and CMOS based Photodetector and Photoreceiver.

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Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

Cited by 5 publications

References 34 publications

Improved Drive Current in RF Vertical MOSFETS Using Hydrogen Anneal

Improved Drive Current in RF Vertical MOSFETS Using Hydrogen Anneal

Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

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