Self-aligned silicon-on-insulator nano flash memory device

Tang, Xiaohui; Baie, X.; Colinge, Jean–Pierre; Crahay, André; Katschmarsyj, B.; Scheuren, V.; Spote, David; Reckinger, Nicolas; Wiele, F. Van de; Bayot, Vincent

doi:10.1016/s0038-1101(00)00221-5

Cited by 24 publications

(6 citation statements)

References 5 publications

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“…Such a device can be fabricated using multigate SOI MOSFET processing techniques. 10,11 The cross section of the fin itself is 8 ϫ 8 nm 2 while the dimensions of the reservoir are 4 ϫ 4 nm 2 . The reservoir is connected to the fin by a 4-nm-deep and 1.5-nm-wide silicon "tunnel."…”

Section: Influence Of Carrier Confinement On the Subthreshold Swing Omentioning

confidence: 99%

Influence of carrier confinement on the subthreshold swing of multigate silicon-on-insulator transistors

Colinge

Afzalian

Lee

et al. 2008

Applied Physics Letters

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The minimum energy of the first conduction subband varies with gate voltage in trigate silicon-on-insulator metal-oxide-silicon field-effect transistors (MOSFETs) in subthreshold operation. In an inversion-mode trigate device, the energy level of the lowest subband increases with electron concentration, while it decreases under the same conditions in some accumulation-mode devices. As a result of this quantum effect, the subthreshold swing of accumulation-mode trigate FETs is smaller than predicted by classical theory. This effect is not observed in fin-shaped FETs and gate-all-around MOSFETs and can be amplified by modifying the device cross section.

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Section: Influence Of Carrier Confinement On the Subthreshold Swing Omentioning

confidence: 99%

Influence of carrier confinement on the subthreshold swing of multigate silicon-on-insulator transistors

Colinge

Afzalian

Lee

et al. 2008

Applied Physics Letters

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“…This section briefly recalls the main process steps since a detailed overview can be found in reference [20]. The critical step corresponds to the implantation through a thin SiO 2 film of a high arsenic dose (1×10 15 cm 2 ).…”

Section: Device Architecture and Processingmentioning

confidence: 99%

Process Optimization and Downscaling of a Single-Electron Single Dot Memory

Krzeminski

Tang

Reckinger

et al. 2009

IEEE Trans. Nanotechnology

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This paper presents the process optimization of a single-electron nanoflash electron memory. Self-aligned single dot memory structures have been fabricated using a wet anisotropic oxidation of a silicon nanowire. One of the main issue was to clarify the process conditions for the dot formation. Based on the process modeling, the influence of various parameters (oxidation temperature, nanowire shape) has been investigated. The necessity of a sharp compromise between these different parameters to ensure the presence of the memory dot has been established. In order to propose an aggressive memory cell, the downscaling of the device has been carefully studied. Scaling rules show that the size of the original device could be reduced by a factor of 2. This point has been previously confirmed by the realization of single-electron memory devices.Index Terms-Device scaling, flash memories, nonvolatile memories, process modeling, quantum dot, scaling limits, silicon-oninsulator (SOI) technology, single-electron device.

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“…[1][2][3][4][5][6][7] These QD structures have been proposed as charge-storage nodes due to their potential applications for future nanoscale memory devices. 8 QD floating gates are regarded as a modern technology that can drastically improve the quality of nonvolatile memory.…”

Section: Introductionmentioning

confidence: 99%

Core–Shell Zn x Cd1−x Se/Zn y Cd1−y Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

Al-Amoody

Suarez

Rodriguez

et al. 2011

Journal of Elec Materi

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This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap Zn y Cd 1Ày Se-cladded Zn x Cd 1Àx Se quantum dots (y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in Zn y Cd 1Ày Se, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II-VI quantum dots as well as two diverse types of devices are presented in this paper.

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Self-aligned silicon-on-insulator nano flash memory device

Cited by 24 publications

References 5 publications

Influence of carrier confinement on the subthreshold swing of multigate silicon-on-insulator transistors

Influence of carrier confinement on the subthreshold swing of multigate silicon-on-insulator transistors

Process Optimization and Downscaling of a Single-Electron Single Dot Memory

Core–Shell Zn x Cd1−x Se/Zn y Cd1−y Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

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