Self-Aligned Wafer-Level Integration Technology With High-Density Interconnects and Embedded Passives

Abstract

This paper presents a polymer-based wafer-level integration technology suitable for integrating RF and mixed-signal circuits and systems. In this technology, disparate dies can be integrated together using a batch fabrication process. Very high density die-to-die interconnects with widths currently as small as 25 m are implemented. To demonstrate the capabilities of this technology, a 10-GHz receiver front-end implemented in 0.18-m CMOS technology is integrated with a high-resistivity Si substrate and embedded passives. By adjusting the input matching of the receiver using the embedded passives fabricated on the high-resistivity Si substrate, the input matching and conversion gain of the front-end receiver are improved.Index Terms-Heterogeneous integration, packaging, systemon-chip (SOC), system-on-package (SIP), wafer-scale integration.

3-D CMOS Circuits Based on Low-Loss Vertical Interconnects on Parylene-N

“…A low-resistivity silicon wafer with bulk resistivity of [10][11][12][13][14][15][16][17][18][19][20] cm is coated with a 5-m-thick thermal silicon dioxide. The bottom metal layer (Metal 1) is a 3.5-m-thick aluminum layer formed by evaporation and lift-off processes.…”

“…Details of the fabrication process is provided in [13]. Since patterns to be post-fabricated on this chip will extend all the way to the edges, and the chip is relatively small in one dimension, a carrier wafer is used to embed this chip in a self-aligned wafer level integration technology discussed in [16]. By employing this technique, handling of the chip becomes easier while the accuracy of the lithography is preserved due to a uniform thickness of photo-resist across the entire chip.…”

Heterogeneous Wafer-Scale Circuit Architectures

“…The potential of using high-density, low-loss interconnects and integrated high-quality passives, in order to complement the advances in high-speed device technology, has been shown to provide maximum benefit for integrated microwave systems. Both design cycle times and system performance have been advanced through the use of high-resistivity Si in a unique Si-based self-aligned wafer-level integration technology (SAWLIT) [7] ( Figure 4) that was developed as part of this project. In this technology, the CMOS or SiGe ICs are integrated within the Si interposer using low-loss interconnects with a definition better than a few micrometers.…”

“…The heterogeneous interposer structure ( Figure 26) uniquely integrates three presently separate technologies. Specifically, an Si substrate that incorporates a number of embedded printed passives and RF interconnects, a high-temperature processed thin-film BST deposited on the substrate, and a multilayer Cu/polymer technology (SAWLIT) that embeds connect lines and passive components [7]. Direct integration of passives into/onto the interposer is utilized to reduce size and improve performance.…”

A Wafer-Scale Rapid Electronic Systems Prototyping Platform

“…Wafer-scale integration feasibility has been demonstrated and several design rules that contribute to make it feasible have been defined as well (Landis, 1990;Boulori, 1991;Anderson, 1992;Koren, 1998;Sharifi, 2007). Moreover fault-tolerance and yield enhancement of WSI have been addressed in (Lea, 1988;Chen, 1994;Moore, 1985) as well as fundamental design methodologies for wafer scale integration in (Hedge, 1991).…”