3-D CMOS Circuits Based on Low-Loss Vertical Interconnects on Parylene-N

Lahiji, Rosa R.; Sharifi, Hasan; Katehi, L.P.B.; Mohammadi, Saeed

doi:10.1109/tmtt.2009.2036394

Cited by 9 publications

(6 citation statements)

References 26 publications

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“…The return loss was more than 15 dB over the frequency of 30 GHz from DC. The insertion loss was in the range of 2.24 to 2.71 dB at 30 GHz, and its average value was 0.25 dB/mm, which was comparable to the insertion loss values of previously reported conventional mmW CPW lines without any bonding technologies [19][20][21]. The deviation of the insertion loss for the twelve CPW lines was within ±10%, which verified that the flip-chip-bonded µ-bump process between the InP-to-SiC substrates was well established, exhibiting good uniformity.…”

Section: Performance Of Flip-chip-bonded Inp-to-sic Cpw Lines Consist...supporting

confidence: 84%

Implementation of Flip-Chip Microbump Bonding between InP and SiC Substrates for Millimeter-Wave Applications

Lee

Song

et al. 2022

Micromachines

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Flip-chip microbump (μ-bump) bonding technology between indium phosphide (InP) and silicon carbide (SiC) substrates for a millimeter-wave (mmW) wireless communication application is demonstrated. The proposed process of flip-chip μ-bump bonding to achieve high-yield performance utilizes a SiO2-based dielectric passivation process, a sputtering-based pad metallization process, an electroplating (EP) bump process enabling a flat-top μ-bump shape, a dicing process without the peeling of the dielectric layer, and a SnAg-to-Au solder bonding process. By using the bonding process, 10 mm long InP-to-SiC coplanar waveguide (CPW) lines with 10 daisy chains interconnected with a hundred μ-bumps are fabricated. All twelve InP-to-SiC CPW lines placed on two samples, one of which has an area of approximately 11 × 10 mm2, show uniform performance with insertion loss deviation within ±10% along with an average insertion loss of 0.25 dB/mm, while achieving return losses of more than 15 dB at a frequency of 30 GHz, which are comparable to insertion loss values of previously reported conventional CPW lines. In addition, an InP-to-SiC resonant tunneling diode device is fabricated for the first time and its DC and RF characteristics are investigated.

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Section: Performance Of Flip-chip-bonded Inp-to-sic Cpw Lines Consist...supporting

confidence: 84%

Implementation of Flip-Chip Microbump Bonding between InP and SiC Substrates for Millimeter-Wave Applications

Lee

Song

et al. 2022

Micromachines

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“…Traditionally, the use of Parylene has appeared routinely as encapsulation layers [11]- [13], isolation layers [14], and structural layers in microelectromechanical systems (MEMS) [15]- [17]. Recently, we proposed a novel all-Parylene packaging concept where Parylene is used as a substrate, an isolation layer, a capacitor insulator, and a passivation layer [18].…”

Section: Introductionmentioning

confidence: 99%

Parylene Interposer as Thin Flexible 3-D Packaging Enabler for Wireless Applications

Maeng

Kim

et al. 2011

IEEE Trans. Microwave Theory Techn.

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This paper presents a novel, all-Parylene, thin, flexible 3-D packaging technology with an application demonstration of wireless powering. Parylene is utilized as a base substrate of a packaging interposer, and multilayer thin films are conformally stacked on the Parylene substrate. High-density (450 pF/mm 2 ) metal-insulator-metal capacitors are implemented with an ultrathin ( 47 nm) deposition of Parylene-N. The energy storage capabilities as well as RF characteristics are characterized. To demonstrate interposer applicability, an RF energy-harvesting study is performed by implementing a rectifier circuit on the Parylene interposer utilizing embedded capacitors of wide-ranging values and an antenna. Finally, substrate folding tests are performed to verify the applicability of the Parylene interposer in a flexible form factor without undergoing degradation in energy-harvesting capability. The thin-film flexible capacitors are demonstrated to not short-circuit even under the stress of folding the interposer.

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“…In CPW, the field interaction with the Si substrate can be reduced by the use of insulators that separate the metal from the substrate [7][8][9]. Substrate interactions with TLs are reduced by applying low loss tangent (tanį), and low permittivity (İ r ) dielectric layers with thicknesses typically greater than 10 µm on top of a low-resistivity Si substrate [5], [10]. Thick dielectric layers have been introduced in literature with an average height of 20 µm that reduce the loss in CPW to reasonable values.…”

Section: Introductionmentioning

confidence: 99%

Minimizing attenuation of coplanar waveguide on lossy silicon substrates up to 300 GHz

Islam

Henderson

2013

2013 IEEE MTT-S International Microwave Symposium Digest (MTT)

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The attenuation constant of coplanar waveguide (CPW), conductor backed CPW (CBCPW) and grounded CPW (GCPW) interconnects is compared up to 300 GHz. Spin-on benzocyclobutene (BCB) dielectric is deposited on low resistivity (10-cm) silicon (Si) substrates to characterize the loss of interconnects at millimeter-wave (mm-wave) frequencies. CPW fabricated on 58 µm of BCB has similar performance as CBCPW and GCPW fabricated on 8.5 µm and 7.6 µm of BCB, respectively. CPW with thick dielectric layers present attenuation of 1.89 dB/mm at 300 GHz, whereas CBCPW and GCPW have an attenuation of 1.87 dB/mm and 1.96 dB/mm, respectively, at the same frequency.

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3-D CMOS Circuits Based on Low-Loss Vertical Interconnects on Parylene-N

Cited by 9 publications

References 26 publications

Implementation of Flip-Chip Microbump Bonding between InP and SiC Substrates for Millimeter-Wave Applications

Implementation of Flip-Chip Microbump Bonding between InP and SiC Substrates for Millimeter-Wave Applications

Parylene Interposer as Thin Flexible 3-D Packaging Enabler for Wireless Applications

Minimizing attenuation of coplanar waveguide on lossy silicon substrates up to 300 GHz

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