This letter presents a resonant tunneling diode (RTD)-based microwave amplifier operating at deep sub-milliwatt level dc-power. The fabricated amplifier, which is based on a reflection-type amplifying topology and uses an InP monolithic microwave integrated circuit technology, shows extremely low dc-power consumption of with a gain of more than 10 dB at 5.7 GHz. The amplifier performance is mainly enabled by the favorable characteristics of the InP-based RTDs biased at . The RTDs exhibit a high peak-to-valley current ratio (PVCR) of 11.2 with a low peak current of and thereby a relatively low negative resistance magnitude of . The dc-power consumption is about 6.4 times lower than that in transistor-based low-power amplifiers reported to date for the 5 GHz frequency band.Index Terms-MMIC amplifiers, negative resistance circuits, quantum effect semiconductor devices, resonant tunneling diodes (RTDs).

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A reflection-type microwave amplifier using InP-based resonant tunnelling diodes (RTDs) has been designed and fabricated. The implemented amplifier shows a low dc-power consumption of 270 μW with RF gains of more than 11 dB at 5.61 GHz. Temperature-dependent characteristics of the RTD amplifier have been investigated at a high temperature. With increasing temperature from 25 to 100°C, the centre frequency shift was measured to be 60 MHz. The RF gains (S 21 /S 12) and the return losses (S 11 /S 22) of the amplifier decreased from 11.45/11.32 and −7.96/−8.11 dB at 25°C to 7.06/6.91 and −11.36/−11.15 dB at 100°C, respectively. The S-parameter degradation phenomena are shown to mainly arise from the temperature dependence of the negative differential resistance (R D) characteristic for the fabricated RTD.

Flip-chip microbump (μ-bump) bonding technology between indium phosphide (InP) and silicon carbide (SiC) substrates for a millimeter-wave (mmW) wireless communication application is demonstrated. The proposed process of flip-chip μ-bump bonding to achieve high-yield performance utilizes a SiO2-based dielectric passivation process, a sputtering-based pad metallization process, an electroplating (EP) bump process enabling a flat-top μ-bump shape, a dicing process without the peeling of the dielectric layer, and a SnAg-to-Au solder bonding process. By using the bonding process, 10 mm long InP-to-SiC coplanar waveguide (CPW) lines with 10 daisy chains interconnected with a hundred μ-bumps are fabricated. All twelve InP-to-SiC CPW lines placed on two samples, one of which has an area of approximately 11 × 10 mm2, show uniform performance with insertion loss deviation within ±10% along with an average insertion loss of 0.25 dB/mm, while achieving return losses of more than 15 dB at a frequency of 30 GHz, which are comparable to insertion loss values of previously reported conventional CPW lines. In addition, an InP-to-SiC resonant tunneling diode device is fabricated for the first time and its DC and RF characteristics are investigated.

This is the first demonstration of sidewall slope control of InP via holes with an etch depth of more than 10 μm for 3D integration. The process for the InP via holes utilizes a common SiO2 layer as an InP etch mask and conventional inductively coupled plasma (ICP) etcher operated at room temperature and simple gas mixtures of Cl2/Ar for InP dry etch. Sidewall slope of InP via holes is controlled within the range of 80 to 90 degrees by changing the ICP power in the ICP etcher and adopting a dry-etched SiO2 layer with a sidewall slope of 70 degrees. Furthermore, the sidewall slope control of the InP via holes in a wide range of 36 to 69 degrees is possible by changing the RF power in the etcher and introducing a wet-etched SiO2 layer with a small sidewall slope of 2 degrees; this wide slope control is due to the change of InP-to-SiO2 selectivity with RF power.