Self calibrating circuit design for variation tolerant VLSI systems

Abstract

Increasing leakage current and aggravating process variations are showing impact on dynamic circuit performance and robustness as technology scales into the nanometer regime. This paper describes a self-calibrating process compensating dynamic (PCD) circuit technique for maintaining the performance benefit of dynamic circuits and reducing the variation in delay and robustness. A variable strength keeper that is optimally programmed based on the die leakage enables 10% faster performance, 35% reduction in delay variation, and 5X reduction in the number of robustness failing dies compared to conventional designs. A new leakage current sensor design is also presented that can detect leakage variation and generate the keeper control signals for the PCD technique. The proposed 6-channel leakage current sensor enables high-resolution on-chip leakage measurements from multiple locations of a die, saving testing cost and realizing both die-to-die and within-die process compensation. Results based on measured leakage data show 1.9-10.2X higher signal-to-noise ratio and reduced sensitivity to supply and P/N skew variations compared to prior leakage sensor designs. The PCD technique with the on-die leakage current sensor is applied to a 2-read, 2-write ported 128x32b register file and a test chip is fabricated in 1.2V, 90nm dual-V t CMOS process.

Probabilistic Approach for Yield Analysis of Dynamic Logic Circuits

“…In order to analyze the variability of a dynamic gate, first we have to study the mean value and standard deviation for the delay time of this transition. So, we can write the time delay to this transition as a function of the random variables of interest (12) and the variance in , using error propagation [16] taking into account circuit symmetry, is given by (13) On the other hand, applying the chain rule, we can conclude by synchronism of variables that , provided that for all what leads to (14) Then, evaluation of transition delay variance for a dynamic-NOR without keeper requires the computation of 9 partial derivatives. These derivatives can be numerically computed using an electrical simulator, according to formulations presented in the Section II-B.…”

“…From these formulas we build the Gaussian probability density function (PDF) provided that we have the necessary parameters (delay calculated at the nominal values) and [computed using formulation (14) or (16)]. …”

“…In [10] a design is presented where the keeper is turned on only if after a given time there is no transition on the dynamic output. Circuit proposed in [14] consists of a 3-bit programmable keeper, where a set of fuses is set during the test phase of the chip. Although recent researches in this area point to self-adaptive dynamic keeper techniques, static keeper is still an industry-standard and largely employed.…”

An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs

“…For the calibration of digital circuits, several voltage keeping [10,11] and body biasing [9,13,14,16,18] approaches exist. However, these methods only target frequency increases and reductions in leakage, delay, and power, thus being of less interest for directly matching transistor pairs in analog and mixed-signal circuits.…”

Designing Robust Checkers in the Presence of Massive Timing Errors

“…For this reason, self-calibration is gaining momentum, both at the device [6] and circuit level [1,12].…”