Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET

Abstract

Abstract-For the rapid adoption of new and aggressive technologies such as ambipolar Silicon NanoWire (SiNW), addressing fault-tolerance is necessary. Traditionally, transient fault detection implies large hardware overhead or performance decrease compared to permanent fault detection. In this paper, we focus on on-line testing and its application to ambipolar SiNW. We demonstrate on self-checking ripple-carry adder how ambipolar design style can help reduce the hardware overhead. When compared with equivalent CMOS process, ambipolar SiNW design shows a reduction in area of at least 56% (28%) with a decreased delay of 62% (6%) for Static (Transmission Gate) design style.

A Survey on Low-Power Techniques with Emerging Technologies

“…In Turkyilmaz et al [2013], a 4-transistor 3-input majority logic gate is proposed and reported here in Figure 11( b). Note that in static CMOS, the same gate has 10 devices in place of 4 [Rabaey et al 2003].…”

Majority-based synthesis for nanotechnologies

“…Specific examples for these nanotechnologies include, but are not limited to, silicon nanowire [1], [2], graphene [3], [4], resistive random-access memory [5], [6], spin-wave devices [7], [8], quantum-dot cellular automata [9], nanomagnets [10], DNA-logic [11], and many others [12]- [14]. We revisit logic synthesis in light of its enabling role in the selection of majority-based nanotechnologies.…”

On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

“…1. Using controllable-polarity devices, it is possible to build very compact arithmetic logic gates, such as eXclusive OR (XOR) [4] and MAJority (MAJ) [15]. For instance, a 2-input XOR gate requires only 4 transistors [4] instead of the 8 required by the traditional full-swing static CMOS implementation [16].…”

“…We will see, in the following, that this introduces a degree of redundancy at the gate level, that is beneficial from a robustness perspective. A selfchecking ripple-carry adder architecture, exploiting this adder structure, is proposed in [15]. This architecture is far less expensive in terms of area than comparable CMOS architectures.…”

“…In this paper, we make one step forward with respect to [15]. In addition to exploit the reduced area cost offered by controllable-polarity devices, we take into account their intrinsic capabilities in masking, i.e., tolerating, faults and use them to build a fault-tolerant adder.…”