Majority-based synthesis for nanotechnologies

Amarù, Luca; Gaillardon, Pierre-Emmanuel; Micheli, Giovanni De

doi:10.1109/aspdac.2016.7428061

Cited by 7 publications

(4 citation statements)

References 22 publications

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“…Recent research [10]- [13] has confirmed that majority logic can implement arithmetic-intensive circuits with fewer gates, and it has been proved that Majority-based logic can achieve up to 33% reduction in logical depth compared to And-based logic [13]. For example, when comparing with IMPLY, the computation efficiency of the mathematical addition doubles with the majority logic, which is one particular case of the threshold logic [14].…”

Section: Introductionmentioning

confidence: 99%

Investigation on the Implementation of Stateful Minority Logic for Future In-Memory Computing

et al. 2021

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Section: Introductionmentioning

confidence: 99%

Investigation on the Implementation of Stateful Minority Logic for Future In-Memory Computing

et al. 2021

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“…Hence, a majority gate is a democratic gate and can be expressed in terms of Boolean AND/OR as M AJ(a, b, c) = a • b + b • c + a • c, where a, b, c are Boolean variables. Although majority logic was known since 1960, there has been a revival in using it for computation in many emerging nanotechnologies (spin waves, magnetic Quantum-Dot cellular automata, nano magnetic logic, Single Electron Tunneling [21]- [23]). Recent research [22]- [25] has confirmed that majority logic is to be preferred not only because a particular nanotechnology can realize it, but also because of its ability to implement arithmetic-intensive circuits with less gates.…”

Section: Introductionmentioning

confidence: 99%

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben

Pechmann

2021

IEEE Trans. VLSI Syst.

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To overcome the 'von Neumann bottleneck', methods to compute in memory are being researched in many emerging memory technologies including Resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/IMPLY logic. In this work, we propose a method to implement a majority gate in a transistoraccessed ReRAM array during READ operation. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant (O(n)). Parallel-prefix adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how parallel-prefix adders can be implemented in memory in O(log(n)) latency. The proposed in-memory addition technique incurs a latency of 4•log(n)+6 for n-bit addition and is energy-efficient due to absence of sneak-currents in 1Transistor-1Resistor configuration.

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“…Although majority logic was known since 1960, there has been a rediscovery in using it for computation in many post-CMOS devices. A majority gate based on spin waves [7], Quantum-Dot cellular automata [8], nano magnetic logic [9], and Single Electron Tunneling [10] have been demonstrated and in some of these technologies, it is more efficient to implement a majority gate [11] than other other logic primitives (NAND, NOR, XOR). Recent research [6,[12][13][14] has confirmed that majority logic is to be preferred not only because a particular nanotechnology can realize it, but also because of its ability to implement arithmetic-intensive circuits with less gates, i.e., in a compact manner.…”

Section: Introductionmentioning

confidence: 99%

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Reuben

2020

JLPEA

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As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

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Majority-based synthesis for nanotechnologies

Cited by 7 publications

References 22 publications

Investigation on the Implementation of Stateful Minority Logic for Future In-Memory Computing

Investigation on the Implementation of Stateful Minority Logic for Future In-Memory Computing

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

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