Self-Measurement of Combinatorial Circuit Delays in FPGAs

Abstract

This article proposes a Built-In Self-Test (BIST) method to accurately measure the combinatorial circuit delays on an FPGA. The flexibility of the on-chip clock generation capability found in modern FPGAs is employed to step through a range of frequencies until timing failure in the combinatorial circuit is detected. In this way, the delay of any combinatorial circuit can be determined with a timing resolution of the order of picoseconds. Parallel and optimized implementations of the method for self-characterization of the delay of all the LUTs on an FPGA are also proposed. The method was applied to Altera Cyclone II and III FPGAs . A complete self-characterization of LUTs on a Cyclone II was achieved in 2.5 seconds, utilizing only 13kbit of block RAM to store the results. More extensive tests were carried out on the Cyclone III and the delays of adder circuits and embedded multiplier blocks were successfully measured. This self-measurement method paves the way for matching timing requirements in designs to FPGAs as a means of combating the problem of process variations.

Characterisation of FPGA Clock Variability

“…7. To estimate the variation due to R, the regional clock routing excluding the cen- tral clock resources, the regional bias was subtracted from the measured results for tests 7 and 8 before calculating the variance (for test 7) or covariance (between tests 7 and 8).…”

“…We have previously reported on the BIST method and circuitry used to achieve accurate signal path delay measurements between registers [7]. The method is summarised below.…”

“…It is therefore necessary to quantify the levels of performance variation exhibited. In our previous work, we reported on measurements of logic and routing variation in FPGAs using ring oscillators [5] and delay measurements using at-speed testing tech- niques [7]. An example of a set of delay measurements made on nominally identical paths using the latter technique is shown in Fig.…”

Time-Bounded Authentication of FPGAs

“…To perform delay characterization, Wong et al in [16] proposed a built-in self-test mechanism for fast chip level delay characterization. The system utilizes the on-chip PLL and DCM modules for clock generation at discrete frequencies.…”

A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture

“…The first category is manufacturer test aiming to make sure the BEs on a chip satisfy the given functional and speed specifications under all the possible reconfiguration options (e.g. [5]). On the other hand, the test in the second category aims to verify whether the mapped application circuit works correctly and it is executed by device users.…”