Self-Selective Resistive Device With Hybrid Switching Mode for Passive Crossbar Memory Application

Wang, Zongwei; Kang, Jian; Bai, Guandong; Zhong, Guofang; Wang, Bowen; Ling, Yaotian; Chen, Qingyu; Bao, Lin; Wu, Lindong; Cai, Yimao; Robertson, John; Huang, Ru

doi:10.1109/led.2020.2992680

Cited by 38 publications

(13 citation statements)

References 30 publications

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“…In addition, the multi-states resistive cell can provide higher precision and density to the CIM architecture [61]. For instance, the resistance of RRAM cell can be changed continuously from KΩ to MΩ between HRS and LRS [62][63][64]. The RRAM-based CIM solution employs an analog-digital converter to identify the different values, hence to implement high-precision MAC operation.…”

Section: Emerging Non-volatile Memory Solutions On Cim Architecturementioning

confidence: 99%

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Chang

Zhang

et al. 2021

Sci. China Inf. Sci.

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An artificial intelligence (AI) processor is a promising solution for energy-efficient data processing, including health monitoring and image/voice recognition. However, data movements between compute part and memory induce memory wall and power wall challenges to the conventional computing architecture. Recently, the memory-centric architecture has been revised to solve the data movement issue, where the memory is equipped with the compute-capable memory technique, namely, computing-in-memory (CIM). In this paper, we analyze the requirement of AI algorithms on the data movement and low power requirement of AI processors. In addition, we introduce the story of CIM and implementation methodologies of CIM architecture. Furthermore, we present several novel solutions beyond traditional analog-digital mixed static random-access memory (SRAM)-based CIM architecture. Finally, recent CIM tape-out studies are listed and discussed.

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Section: Emerging Non-volatile Memory Solutions On Cim Architecturementioning

confidence: 99%

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Chang

Zhang

et al. 2021

Sci. China Inf. Sci.

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“…Note that the same design can be extended to other NVM technologies, such as STT-MRAM [16], FeFET [17], etc. Logic values are stored as the resistance of the memory cells, which can be switched between two or more levels [18,19] by applying electrical excitation with different amplitudes and duration. The NVM cells are arranged with a structure of crossbar, which has been widely used to perform VMM [20].…”

Section: Backgrounds 21 Nvpim Acceleratormentioning

confidence: 99%

MobiLatice

Zheng

Wang

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…The self-selected device (SSD) is the only way to overcome sneak current in 3D vertical integration. The currently reported SSDs, which are based on interface barrier modulation, possess good uniformity but poor retention performance [17][18][19][20]. Retention failures have an adverse impact on the overall accuracy of the implemented neural network, which worsens when the device operates at high temperatures during edge computing [11].…”

Section: Introductionmentioning

confidence: 99%

Long-Term Accuracy Enhancement of Binary Neural Networks Based on Optimized Three-Dimensional Memristor Array

Zhang

Dong

et al. 2022

Micromachines

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In embedded neuromorphic Internet of Things (IoT) systems, it is critical to improve the efficiency of neural network (NN) edge devices in inferring a pretrained NN. Meanwhile, in the paradigm of edge computing, device integration, data retention characteristics and power consumption are particularly important. In this paper, the self-selected device (SSD), which is the base cell for building the densest three-dimensional (3D) architecture, is used to store non-volatile weights in binary neural networks (BNN) for embedded NN applications. Considering that the prevailing issues in written data retention on the device can affect the energy efficiency of the system’s operation, the data loss mechanism of the self-selected cell is elucidated. On this basis, we introduce an optimized method to retain oxygen ions and prevent their diffusion toward the switching layer by introducing a titanium interfacial layer. By using this optimization, the recombination probability of Vo and oxygen ions is reduced, effectively improving the retention characteristics of the device. The optimization effect is verified using a simulation after mapping the BNN weights to the 3D VRRAM array constructed by the SSD before and after optimization. The simulation results showed that the long-term recognition accuracy (greater than 105 s) of the pre-trained BNN was improved by 24% and that the energy consumption of the system during training can be reduced 25,000-fold while ensuring the same accuracy. This work provides high storage density and a non-volatile solution to meet the low power consumption and miniaturization requirements of embedded neuromorphic applications.

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Self-Selective Resistive Device With Hybrid Switching Mode for Passive Crossbar Memory Application

Cited by 38 publications

References 30 publications

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

MobiLatice

Long-Term Accuracy Enhancement of Binary Neural Networks Based on Optimized Three-Dimensional Memristor Array

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