SEM-based methodology for root cause analysis of wafer edge and bevel defects

Porat, Ronnie; Dotan, Kfir; Hemar, Shirley; Levin, L. S.; Li, K.; Sung, Gun Yong

doi:10.1109/asmc.2008.4528998

Cited by 6 publications

(1 citation statement)

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“…[10] The important approach to raising IC yield related to random defects is to optimize the IC layout in the IC design stage, especially in the layout design stage, which depends on the information about the random defects causing yield loss. [11][12][13][14] The existing experimental results show that the real defects are of irregular shape, [15][16][17][18] and that these defects have a certain space distribution. [19][20][21] In order to describe the yield loss in the IC manufacturing stage, a concept of the critical area in an IC layout and its extraction method are presented.…”

Section: Introductionmentioning

confidence: 99%

Open critical area model and extraction algorithm based on the net flow-axis

Wang

Gao

et al. 2013

Chinese Phys. B

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In the integrated circuit manufacturing process, the critical area extraction is a bottleneck to the layout optimization and the integrated circuit yield estimation. In this paper, we study the problem that the missing material defects may result in the open circuit fault. Combining the mathematical morphology theory, we present a new computation model and a novel extraction algorithm for the open critical area based on the net flow-axis. Firstly, we find the net flow-axis for different nets. Then, the net flow-edges based on the net flow-axis are obtained. Finally, we can extract the open critical area by the mathematical morphology. Compared with the existing methods, the nets need not to divide into the horizontal nets and the vertical nets, and the experimental results show that our model and algorithm can accurately extract the size of the open critical area and obtain the location information of the open circuit critical area.

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