SEM-based overlay measurement between via patterns and buried M1 patterns using high-voltage SEM

Hasumi, Kazuhisa; Ito, Osamu; Okagawa, Yutaka; Shao, Chuanyu; Leray, Philippe; Halder, Sandip; Lorusso, Gian; Jehoul, Christiane

doi:10.1117/12.2257848

Cited by 9 publications

(7 citation statements)

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“…SEMs are also used with other techniques 47,5354 (see hybrid metrology below) to obtain information on parts of a feature that cannot be measured directly. SEM is used for overlay measurements, and high voltage SEM has been proposed as a viable candidate for overlay of buried layers 47,55 ; and contour metrology, where the required information are planar two-dimensional profiles used to verify optical proximity correction 56,57…”

Section: Advanced Metrology Techniquesmentioning

confidence: 99%

Metrology for the next generation of semiconductor devices

Badaroglu²,

et al. 2018

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The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre-scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution.

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Section: Advanced Metrology Techniquesmentioning

confidence: 99%

Metrology for the next generation of semiconductor devices

Badaroglu²,

et al. 2018

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“…With the continuous shrink in pattern size and increased density, overlay and edge-placement [13][14][15][16][17] control has become one of the most critical issues in semiconductor manufacturing. In particular, there is a clear need for SEMbased overlay measurements of after develop inspection (ADI) wafers, to serve as reference for optical overlay and make the necessary corrections before etching.…”

Section: Sem-based Overlay Measurement Between Resist and Buried Patt...mentioning

confidence: 99%

Electron beam metrology for advanced technology nodes

Lorusso

Horiguchi

Bömmels

et al. 2019

Jpn. J. Appl. Phys.

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The critical dimension scanning electron microscope (CD-SEM) is one of the main tools used to estimate critical dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in of morphology and chemical composition as well. In fact, complicated three-dimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. In this paper, we report on the development of advanced CD-SEM metrology at imec on a variety of device platforms and processes, for both logics and memories. The large variety of results reported here a clear indication of the on-going creative effort needed to ensure that the critical potential of CD-SEM metrology tools is fully enabled for the 5 nm node and beyond.

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“…Recent studies have demonstrated that HV-SEM can reduce residual overlay errors that cannot be fully resolved by optical overlay measurement, showing its capability as an on-device overlay metrology tool [4,5,6]. In general, HV-EBI tool-based on-device overlay measurements are susceptible to biases from image distortion and beam perpendicularity, which can result in significant errors during mask modification or process correction.…”

Section: Introductionmentioning

confidence: 99%

Advanced high-voltage e-beam system combined with an enhanced D2DB for on-device overlay measurement

Kang¹,

Maruyama²,

Yamazaki³

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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High voltage scanning electron microscopy (HV-SEM) has recently been adopted as an on-device overlay metrology tool. However, the chip-manufacturing industry requests more advanced tools capable of low-distortion imaging and versatile measurement functionality for multi-layer processing. We developed a high voltage e-beam inspection (HV-EBI) tool for on-device overlay metrology that fills the abovementioned requirement. The HV-EBI tool has the capability of variable acceleration voltage in the range of 30kV to 50kV and wide field of view (FOV) imaging up to a maximum of 50μm with extremely low first-order distortion in the level of <0.01% and 0.1mrad and uniform in-plane beam perpendicularity. In this paper, we demonstrate the performance of on-device overlay measurement by using the proposed HV-EBI tool combined with enhanced die-to-database (D2DB) algorithm and image processor.

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SEM-based overlay measurement between via patterns and buried M1 patterns using high-voltage SEM

Cited by 9 publications

References 0 publications

Metrology for the next generation of semiconductor devices

Metrology for the next generation of semiconductor devices

Electron beam metrology for advanced technology nodes

Advanced high-voltage e-beam system combined with an enhanced D2DB for on-device overlay measurement

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