Semi-parallel reconfigurable architectures for real-time LDPC decoding

Abstract

This paper presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC)

Task Parallel Implementation of Belief Propagation in Factor Graphs

“…However, while these techniques are proposed for general factor graphs which lead to approximate inference, we focus on acyclic factor graphs for exact inference. In digital communications, parallel belief propagation is implemented on FPGAs, GPUs, and multi-core processors [27], [8]. Similar to [7], these techniques apply to cyclic factor graphs with the employment of embarrassingly parallel algorithms.…”

VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax

“…In a VLSI implementation, this property greatly simplifies the logic and reduces the memory. Since only the two least minimum numbers need to be identified, the number of comparisons can be reduced, while in the CNU proposed in [8], 2k comparators are used to compute (3) associated with that check node. We present efficient serial implementations for CNU.…”

“…Note that we need to store partial state for only one block row at any time. In the decoding process, a block row of check nodes are processed in serial fashion using M CNUs as in (8), the output of the CNU is also in serial form. The CNU array will start the partial state computation for next block row as soon as the partial state processing for the previous block row is done.…”

“…So the savings are around 91% as 19 max = k and, z 0 =96 for block LDPC codes in 802.16e. The total savings in memory accounting for R memory, Q memory, and P memory, when compared to TPMP architectures based on SP [13] and min-sum [7], [8], [14] is 63%.When compared to TDMP architecture based on BCJR [2], the total memory savings is 55% since both architectures have the same savings in Q memory. In terms of throughput and interconnect advantage, to achieve the same BER as that of TPMP schedule on OMS, R selection for R new operates out-of-order to feed the data for PS processing of next layer TDMP schedule on OMS needs half the number of iterations.…”

LDPC code design for OFDM channel: graph connectivity and information bits positioning

“…Among the different existing codes, Low Density Parity-Check (LDPC) present a great interest for COFDM transmission, as shown for instance in [3]. Much attention is being given to LDPC codes due to their excellent performance and the simplicity of iterative decoding making high throughput possible [2]. It has been shown in [4], that for an OFDM transmission, the optimization of the LDPC code accordingly with the channel spectrum provides large performance gain with no reduction of 1 This work was supported in part by Nokia Corporation, Texas Instruments Inc., and by NSF under grants ANI-9979465, EIA-0224458, and EIA-0321266.…”