Semiconductor measurement technology

Abstract

This progress report describes NBS activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices. Both in-house and contract efforts are included. The emphasis is on silicon device technologies. Principal accomplishments during this reporting period included (1) preliminary results of a systematic study of the effects of surface preparation on spreading resistance measurements; (2) development of an optical test for surface quality of sapphire; (3) development of a basis for an exposure sensitivity specification for photoresists; and (4) development of a modular cell concept for test structure design and layout. Also reported are the results of work on four-probe resistivity measurements, comparison of techniques for surface analysis, ion microprobe mass analysis, analysis of process chemicals with flame emission spectrometry, redistribution profiles, thermally stimulated current response of interface states, bias-temperature stress test measurements on MOS capacitors, a high voltage capacitance-voltage method for measuring characteristics of thick insulator films, hydrogen chloride oxidation, ion implantation parameters, methods for determining integrity of passivation overcoats, measurement of free sodium in an oxidation furnace by resonance fluorescence, a square array collector resistor test structure, an electrical alignment test structure, two dimensional wafer maps, test pattern design and analysis for silicon-on-sapphire MOS device technologies^a nondestructive acoustic emission test for beam-lead bonds, wire bond pull test, bondability of doped aluminum metallizations, leakage into double hermetic enclosures, a static expansion dry gas gross leak test, correlation of moisture infusion in semiconductor packages with leak size and device reliability, an automated scanning lowenergy electron probe, an optical flying-spot scanner, scanning electron microscopy, scanning acoustic microscopy, and thermal resistance measurements on power transistors and simple integrated circuits. Supplementary data concerning staff, publications, workshops and symposia, standards committee activities, and technical services are also included as appendices.

Test patterns NBS-28 and NBS-28A

“…The random fault structures on test patterns NBS-28 and NBS-28A are intended to assess the capability of a process to produce a single level of fault-free metal interconnects as a function of area and as a function of linewidth and spacing. The present structure configuration is an extension of the random fault step coverage test structure on test pattern NBS-7 [3][4][5] redesigned to include more steps with smaller dimensions, and to permit investigation of methods of testing and data analysis in more detail.…”