SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs

Ghaderi, Zana; Ebrahimi, Mohammad; Navabi, Zainalabedin; Bozorgzadeh, Eli; Bagherzadeh, Nader

doi:10.1109/tc.2016.2622688

Cited by 24 publications

(12 citation statements)

References 20 publications

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“…Other previously proposed countermeasures include glitch detectors [28], aging sensors [29], [30], shadow registers [31], and razor latches [32]. Assuming that all one knows about the victim is its critical path delay, we design a lightweight countermeasure illustrated in Fig.…”

Section: A Background and Related Workmentioning

confidence: 99%

X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs

Mahmoud

Stojilović

2020

2020 30th International Conference on Field-Programmable Logic and Applications (FPL)

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Albeit very appealing, FPGA multitenancy in the cloud computing environment is currently on hold due to a number of recently discovered vulnerabilities to side-channel attacks and covert communication. In this work, we successfully demonstrate a new attack scenario on shared FPGAs: we show that an FPGA tenant can activate a dormant hardware Trojan without any physical or logical connection to the private Trojan-infected FPGA circuit. Our victim contains a so-called satisfiability don't-care Trojan, activated by a pair of don't-care signals, which never reach the combined trigger condition under normal operation. However, once a malicious FPGA user starts to induce considerable fluctuations in the on-chip signal delaysand, consequently, the timing faults-these harmless don't-care signals take unexpected values which trigger the Trojan. Our attack model eliminates the assumption on physical access to or manipulation of the victim design. Contrary to existing fault and side-channel attacks that target unprotected cryptographic circuits, our new attack is shown effective even against provably well-protected cryptographic circuits. Besides demonstrating the attack by successfully leaking the entire cryptographic key from one unprotected and one masked AES S-box implementation, we present an efficient and lightweight countermeasure.

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Section: A Background and Related Workmentioning

confidence: 99%

X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs

Mahmoud

Stojilović

2020

2020 30th International Conference on Field-Programmable Logic and Applications (FPL)

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“…TEP circuits [1][2][3][4][5][6] predict a potential error by monitoring data signals. It flags a warning signal whenever the delayed data signals enter an erroneous timing zone that is defined with a clock signal.…”

Section: Introductionmentioning

confidence: 99%

A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

2020

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Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

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“…In contrast, the current paper targets in-the-field mitigation, which can be applied multiple times during the lifetime of a chip, even at user level, without the vendor's support. Additionally, inthe-field mitigation enables dynamic adaptation to environmental and aging effects that degrade system performance erratically [12]. The industry has acknowledged the benefits of such mitigation and the need for relevant IPs [13].…”

Section: Introductionmentioning

confidence: 99%

In-the-Field Mitigation of Process Variability for Improved FPGA Performance

Maragos

Lentaris²,

Soudris³

2019

IEEE Trans. Comput.

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The mitigation of process variability becomes paramount as chip fabrication advances deeper into the sub-micron regime. Conservative guard-bands result in considerable performance loss, while most low-level solutions impede dynamic customization at application level. This paper exploits the existing process variability of commercial off-the-shelf FPGAs to improve the operating frequency of a design, in-the-field, at anytime during the lifetime of a chip. We begin by measuring variability in prevalent FPGAs and assessing its impact on the performance of common DSP benchmarks. For the former, we develop a custom sensing network of Ring-Oscillators to generate detailed 2D maps per chip. For the latter, we perform intensive testing and statistical analysis to establish the relation between variability maps and benchmark frequencies. Accordingly, we propose a framework to automatically characterize the user's devices, place the design on the most efficient region, and scale its frequency based on user requirements and functional verification. Experimental results on 20 FPGAs of 28 nm Xilinx technology show up to 13 percent intra-die and 30 percent inter-die variability; with limited cost, our framework provides 10À14.7 percent average gain by exploiting such variability, or up to 56À138 percent by also customizing the guard-band.

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SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs

Cited by 24 publications

References 20 publications

X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs

X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs

A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

In-the-Field Mitigation of Process Variability for Improved FPGA Performance

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