Sensor-Less Logic-Equation-Based Modualtion Method for Grid-Connected PUC5 Converter

Reliability and Performance Improvement of PUC Converter Using a New Single-Carrier Sensor-Less PWM Method With Pseudo Reference Functions

“…Hence, among other suggested MLCs, the PUC converter is more competitive, especially for single-phase applications. Various modulation and control methods have been presented for the PUC converter to provide suitable output voltage and regulate the dc capacitor voltage to a desired value [6][7][8][9][10][11][12][13].…”

“…In [9][10][11][12][13], the sensor-less carrier-based PWM switching methods has been presented for the PUC converter. In [9], a phase disposition PWM (PDPWM) method with sensor-less control of the dc capacitor voltage has been introduced for the PUC converter.…”

“…Moreover, the presented method in [9] needs a switching states table, six If-Else loops, as well as five logic gates, and the suggested method in [11] requires twelve If-Else loops. Furthermore, in suggested methods in [9][10][11], charging/discharging of the dc capacitor is balanced in each fundamental period of the output voltage [12,13]. Therefore, by applying the presented methods in [9][10][11] to the PUC converter, the size and voltage ripple of the dc capacitor depend on the output voltage fundamental frequency and the load current.…”

“…Consequently, a large dc capacitor is required to form a suitable output voltage waveform. Sensor-less modulation methods using two level-shifted PWM carriers and logic gates have been presented in [12] and [13]. In presented methods in [12] and [13], not only the number of required PWM carrier signals is halved, but also the size of the dc capacitor is reduced by balancing charging/discharging of the dc capacitor in each PWM period.…”

“…Sensor-less modulation methods using two level-shifted PWM carriers and logic gates have been presented in [12] and [13]. In presented methods in [12] and [13], not only the number of required PWM carrier signals is halved, but also the size of the dc capacitor is reduced by balancing charging/discharging of the dc capacitor in each PWM period. However, they require two level-shifted PWM carrier signals, five comparators, and six logic gates.…”