Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling

Vandooren, A.; Witters, L.; Franco, J.; Mallik, Arindam; Parvais, B.; Wu, Z.; Walke, A.; Deshpande, V.; Rosseel, Erik; Hikavyy, Andriy; Li, W.; Peng, Lan; Rassoul, Nouredine; Jamieson, Geraldine; Inoue, Fumihiro; Verbinnen, Greet; Devriendt, K.; Teugels, Lieve; Heylen, N.; Vecchio, E.; Zheng, T.; Waldron, Niamh; Heyn, V. De; Mocuta, D.; Collaert, N.

doi:10.1109/icicdt.2018.8399777

Cited by 13 publications

(5 citation statements)

References 4 publications

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“…Ultra-fast laser annealing techniques are being explored as a way to achieve high dopant activation with minimal diffusion in ion implanted junctions, without affecting underlying buried layers in 3D integrated devices [23,24]. These techniques are opening a new window of processing conditions, where localized zones of the Si substrate are heated at temperatures close to the melting point for just tens of nanoseconds.…”

Section: Introductionmentioning

confidence: 99%

{001} loops in silicon unraveled

et al. 2019

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By using classical molecular dynamics simulations and a novel technique to identify defects based on the calculation of atomic strain, we have elucidated the detailed mechanisms leading to the anomalous generation and growth of {001} loops found after ultra-fast laser annealing of ion-implanted Si. We show that the building block of the {001} loops is the very stable Arai tetra-interstitial [N. Arai, S. Takeda, M. Kohyama, Phys. Rev. Lett. 78, 4265 (1997)], but their growth is kinetically prevented within conventional Ostwald ripening mechanisms under standard processing conditions. However, our simulations predict that at temperatures close to the Si melting point, Arai tetra-interstitials directly nucleate at the boundaries of fast diffusing selfinterstitial agglomerates, which merge by a coalescence mechanism reaching large sizes in the nanosecond timescale. We demonstrate that the crystallization of such agglomerates into {001} loops and their subsequent growth is mediated by the tensile and compressive strain fields that develop concurrently around the loops. We also show that further annealing produces the unfaulting of {001} loops into perfect dislocations. Besides, from the simulations we have fully characterized the {001} loops, determining their atomic structure, interstitial density and formation energy.

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Section: Introductionmentioning

confidence: 99%

{001} loops in silicon unraveled

et al. 2019

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“…The process flow of Schottky S/D FinFETs is summarized in Figure 1 a. SOI wafers measuring 200 mm with top Si of 40 nm and BOX of 145 nm were used as the starting materials to mimic the bonded substrate of top-tier devices. The replacement metal gate (RMG) process was adopted, and all process steps were set below the typical thermal budget of 550 °C for compatibility with 3D sequential integration [ 3 , 4 , 5 ]. According to the principle of Schottky S/D MOSFETs [ 18 ], the electrical property is primarily determined by the Schottky junction barrier between S/D and channel.…”

Section: Device Fabricationmentioning

confidence: 99%

“…This technology can enhance circuit density and functionality without the requirement of further reduction in device dimensions. To maintain the integrity of what is below, namely the bottom devices, interconnections and bonding interface, the thermal budget for top-tier fabrication is required to be no more than 550 °C [ 3 , 4 , 5 ].…”

Section: Introductionmentioning

confidence: 99%

Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration

Mao

Gao

et al. 2022

Nanomaterials

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In this work, low-temperature Schottky source/drain (S/D) MOSFETs are investigated as the top-tier devices for 3D sequential integration. Complementary Schottky S/D FinFETs are successfully fabricated with a maximum processing temperature of 500 °C. Through source/drain extension (SDE) engineering, competitive driving capability and switching properties are achieved in comparison to the conventional devices fabricated with a standard high-temperature (≥1000 °C) process flow. Schottky S/D PMOS exhibits an ON-state current (ION) of 76.07 μA/μm and ON-state to OFF-state current ratio (ION/IOFF) of 7 × 105, and those for NMOS are 48.57 μA/μm and 1 × 106. The CMOS inverter shows a voltage gain of 18V/V, a noise margin for high (NMH) of 0.17 V and for low (NML) of 0.43 V, with power consumption less than 0.9 μW at VDD of 0.8 V. Full functionality of CMOS ring oscillators (RO) are further demonstrated.

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“…Another interesting structure being investigated to replace the copper interconnect is a carbon nanotube [5], [6]. However, integrating a completely novel structure and material is complex and the accepted reality is that we will live with copper for the foreseeable future, at least down to the 3nm node [7]. Ultimately, copper is expected to continue to be used for the next several technology nodes [4], [8], possibly in combination with cobalt at the M0 and M1 layers and on its own in higher metal stacks.…”

Section: Introductionmentioning

confidence: 99%

Microstructure and Granularity Effects in Electromigration

Filipovic

Selberherr

2021

IEEE J. Electron Devices Soc.

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The persistent advancements made in the scaling and vertical implementation of front-end-of-line transistors has reached a point where the back-end-of-line metallization has become the bottleneck to circuit speed and performance. The continued scaling of metal interconnects at the nanometer scale has shown that their behavior is far from that expected from bulk films, primarily due to the increased influence that the microstructure and granularity plays on the conductive and electromigration behavior. The impact of microstructure is noted by a sharp shift in the changing crystal orientation at the grain boundaries and the roughness introduced at the interfaces between metal films and the surrounding dielectric or insulating layers. These locations are primary scattering centers of conducting electrons, impacting a film's electrical conductivity, but they also impact the diffusion of atoms through the film during electromigration. Therefore, being able to fully understand and model the impact of the microstructure on these phenomena has become increasingly important and challenging, because the boundaries and interfaces must be treated independently from the grain bulk, where continuum simulations become insufficient. In light of this, recent advances in modeling electromigration in nanometer sized copper interconnects are described, which use spatial material parameters to identify the locations of the grain boundaries and material interfaces. This method reproduces the vacancy concentration in thin copper interconnects, while allowing to study the impact of grain size and microstructure on copper interconnect lifetimes.

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Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling

Cited by 13 publications

References 4 publications

{001} loops in silicon unraveled

{001} loops in silicon unraveled

Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration

Microstructure and Granularity Effects in Electromigration

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