Sequential circuit verification using symbolic model checking

Abstract

The temporal logic model checking algorithm developed by Clarke, Emerson, and Sistla [9] is modified to represent a state graph using Binary decision diagrams (BDD's) [4]. B ecause this representation captures some of the regularity in the state space of sequential circuits with data path logic, we are able to verify circuits with an extremely large number of states. We demonstrate this new technique on a synchronous pipelined design with approximately 5 x 10zo states. Our model checking algorithm handles full CTL with fairness constraints. Consequently, we are able to handle a number of important liveness and fairness properties, which would otherwise not be expressible in CTL. We give empirical results on the performance of the algorithm applied to both synchronous and asynchronous circuits with data path logic.

BDD-Based Software Model Checking with CPAchecker

“…Binary decision diagrams (BDD) [10] are an efficient data structure for manipulation of large sets, because they represent the sets in a compressed representation, and operations are performed directly on the compressed representation. BDDs are used, for example, to store the state sets in tools for hardware verification [11,12], for transition systems in general [16], for real-time systems [8,13], and push-down systems [14]. There are programming systems for relational programming [2] based on BDDs, and the data structure is used for points-to program analyses [1].…”

Verifying Statemate Statecharts Using CSP and FDR

“…Clarke and his colleagues have developed the SMV tool for checking finite state systems against specifications in the temporal logic CTL [4][5][6]. Work by Bienmuller, Damm and their colleagues has built up the STVE to model and verify some industrial applications [2,3,7,11].…”

Formally Verifying Data and Control with Weak Reachability Invariants

“…Model checking [6,5,4] the full design is infeasible because of the large amount of state in the data path. Verifying the control FSMs in isolation is difficult, because specifying them independently is difficult -the design requirements are usually stated as properties of the data path, not the FSMs themselves.…”