Serial-to-Parallel Converter Using GaAs D-Mode Transistors

GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips

“…The super buffered FET logic (SBFL) has been also proposed, which favors instead noise margins and achieves moderate speed, comparable to DCFL. The buffered FET logic (BFL) is the preferred choice when depletionmode (D-mode) transistors are only available, or when they are deliberately exploited either to enhance speed or to allow higher RF operating frequencies for the analog portion of the CC [28,32]. Only two flip-flop architectures are present in the literature, which will be discussed in Section 6, even if in many works such a detail is not available, as well as the clock speed.…”

“…Only two flip-flop architectures are present in the literature, which will be discussed in Section 6, even if in many works such a detail is not available, as well as the clock speed. The latter indeed is not a stringent design constraint, and is thus typically in the range of tens of megahertz, except for [32] where a simultaed bit rate of 3 Gbit/s is reported.…”

“…All these parameters are interdependent, thus achieving the best trade-off among them is a main design challenge and the most suitable implementation depends on the case, based on which one of these features has to be favored. Most of the SIPO examples available in the literature adopt the same DFFs for the SR and the HR [20,24,25,27,29,31,32]. This choice is surely the most convenient in terms of design effort and modularity, since, once the DFF cell is optimized, it is just replicated 2n times to create the two n-bit registers.…”

“…Fortunately, since the late 90s, the current handling capability of the integrated resistors was significantly improved, and very high sheet resistance values were achieved, which allow the implementation of high value resistors (HVRs) with very compact layouts. The use of HVRs in place of diodes for level-shifting overcomes their limitations and offers the possibility to trade-off between power consumption and noise margins according to the specific design requirement [28,32].…”

“…Being based on series combination, the NAND is faster and shows lower current consumption than the NOR, but, on the other hand, it implies voltage stacking, which may rise too much the overall output voltage with consequent interfacing issues with the following stage. When three inputs are needed, the NOR option is thus preferred, even if in [32] a three-input NAND was exploited to reach an impressive bit-rate thanks to the lower latency. The sensitivity to the transistor voltage threshold is still a major concern in both unbuffered and buffered logic families.…”