Serialized asynchronous links for NoC

Ogg, S.; Valli, Enrico; Al-Hashimi, Bashir M.; Yakovlev, Alex; D'Alessandro, C.; Benini, Luca

doi:10.1145/1403375.1403617

Cited by 5 publications

(1 citation statement)

References 11 publications

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“…The theory and practice of NoC development has been steadily increasing every year. There are a large number of different solutions at the level of synchronization of NoC communication subsystem [3,4,5], communication technology [5,6,7], connecting links organization [8], routers organization (packet-level connection technology [2,9], route search algorithms [10], flow control [11]), and NoCs quality-of-service (QoS) arbitrage [2,4,9]. The analysis of this wide range of solutions shows that the most common NoCs are synchronous [3] or GALS networks [5] with packet communication, distributed generation of destination addresses, wormhole/virtual channels [12] with packet-level connection and the availability of QoS mechanisms [4].…”

Section: Introductionmentioning

confidence: 99%

Development of routing algorithms in networks-on-chip based on ring circulant topologies

Romanov

2019

Heliyon

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This work is devoted to the study of communication subsystem of networks-on-chip (NoCs) development with an emphasis on their topologies. The main characteristics of NoC topologies and the routing problem in NoCs with various topologies are considered. It is proposed to use two-dimensional circulant topologies for NoC design, since they have significantly better characteristics than most common mesh and torus topologies, and, in contrast to many other approaches to improving topologies, have a regular structure. The emphasis is on using ring circulants which although in some cases have somewhat worse characteristics than the optimal circulants, compensate by one-length first generatrix in such graphs that greatly facilitate routing in them. The paper considers three different approaches to routing in NoCs with ring circulant topology: Table routing, Clockwise routing, and Adaptive routing. The algorithms of routing are proposed, the results of synthesis of routers, based on them, are presented, and the cost of chip resources for the implementation of such communication subsystems in NoCs is estimated.

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Section: Introductionmentioning

confidence: 99%

Development of routing algorithms in networks-on-chip based on ring circulant topologies

Romanov

2019

Heliyon

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Asynchronous Current Mode Serial Communication

Dobkin

Moyal

Kolodny

et al. 2010

IEEE Trans. VLSI Syst.

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Abstract-An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the differential level encoded dual-rail (LEDR) two-phase asynchronous protocol, avoiding per-bit handshake and eliminating per-bit synchronization, in contrast with synchronous serial links that rely on complex clock recovery. Novel low-power current signaling driver and receiver circuits are presented, enabling high-speed communication at a very low voltage swing over long wires. In contrast, previous methods employed voltage sensing, resulting in higher swing, higher dynamic power, shorter wires or slower operation. The asynchronous current mode driver is designed to support varying data rates, and it eliminates the need for balanced codes and busy toggling that prevent deep discharge. The data cycle time of the link is equal to a single gate delay, enabling 67 Gb/s throughput in 65-nm technology. Wave-pipelining is employed also by the asynchronous SERDES circuits, to enable such high speed operation. The link was SPICE simulated for 65-nm technology, using wire models obtained by a 3-D EM solver. The link incurs lower power and area relative to synchronous and asynchronous bit-parallel communications, and these relative benefits also scale with technology.

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Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs

Sun

Cevrero

Athanasopoulos

et al. 2010

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip

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Abstract-This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced by serialized links to save silicon area and increase yield. Detailed analysis conducted in 90 nm CMOS technology shows that the proposed 2-Gb/s/pin quasi-serial link requires approximately five times less area than its parallel bus equivalent at same data rate for a TSV diameter of 20 μm.

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Serialized asynchronous links for NoC

Abstract: Abstract

Cited by 5 publications

References 11 publications

Development of routing algorithms in networks-on-chip based on ring circulant topologies

Development of routing algorithms in networks-on-chip based on ring circulant topologies

Asynchronous Current Mode Serial Communication

Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs

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