Servet: A benchmark suite for autotuning on multicore clusters

González-Domínguez, Jorge; Taboada, Guillermo L.; Fraguela, Basilio B.; Martín, María J.; Touriño, Juan

doi:10.1109/ipdps.2010.5470358

Cited by 18 publications

(16 citation statements)

References 18 publications

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“…The other related works have different focuses with ours. P-Ray [6] and Servet [7] characterized sharing and communication aspects of multi-core clusters. Taylor et al [9] extended memory characterization techniques to AMD GPUs.…”

Section: Related Workmentioning

confidence: 99%

Efficient Characterization of Hidden Processor Memory Hierarchies

Cooper

2018

Lecture Notes in Computer Science

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A processor's memory hierarchy has a major impact on the performance of running code. However, computing platforms, where the actual hardware characteristics are hidden from both the end user and the tools that mediate execution, such as a compiler, a JIT and a runtime system, are used more and more, for example, performing large scale computation in cloud and cluster. Even worse, in such environments, a single computation may use a collection of processors with dissimilar characteristics. Ignorance of the performance-critical parameters of the underlying system makes it difficult to improve performance by optimizing the code or adjusting runtime-system behaviors; it also makes application performance harder to understand. To address this problem, we have developed a suite of portable tools that can efficiently derive many of the parameters of processor memory hierarchies, such as levels, effective capacity and latency of caches and TLBs, in a matter of seconds. The tools use a series of carefully considered experiments to produce and analyze cache response curves automatically. The tools are inexpensive enough to be used in a variety of contexts that may include install time, compile time or runtime adaption, or performance understanding tools.

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Section: Related Workmentioning

confidence: 99%

Efficient Characterization of Hidden Processor Memory Hierarchies

Cooper

2018

Lecture Notes in Computer Science

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“…The computation phase corresponds to a two nested loops that scans a vector of integers in steps of 1K bytes, so that hardware prefetching is avoided, since the step size is bigger than any cache line and also the cache size is a multiple of this step size [41]. The manner in which the vector is accessed also avoids further optimizations carried out by the compiler, as discussed in [40].…”

Section: On Modeling Multicore Clustersmentioning

confidence: 99%

Memory aware load balance strategy on a parallel branch‐and‐bound application

Silva

Boeres

Drummond

et al. 2014

Concurrency and Computation

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SUMMARYThe latest trends in high-performance computing systems show an increasing demand on the use of a large scale multicore systems in a efficient way, so that high compute-intensive applications can be executed reasonably well. However, the exploitation of the degree of parallelism available at each multicore component can be limited by the poor utilization of the memory hierarchy available. Actually, the multicore architecture introduces some distinct features that are already observed in shared memory and distributed environments. One example is that subsets of cores can share different subsets of memory. In order to achieve high performance it is imperative that a careful allocation scheme of an application is carried out on the available cores, based on a scheduling model that considers the main performance bottlenecks, as for example, memory contention. In this paper, the Multicore Cluster Model (MCM) is proposed, which captures the most relevant performance characteristics in multicores systems such as the influence of memory hierarchy and contention. Better performance was achieved when a load balance strategy for a Branch-and-Bound application applied to the Partitioning Sets Problem is based on MCM, showing its efficiency and applicability to modern systems.

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“…RELATED WORK Our automatic computer system characterization project [1] has employed the X-Ray tool and methodology [11], [12] and the Servet tool [13] to collect data from performance measurements using microbenchmarks. System characterization information that is useful for a parallelizing compiler , such as cache sizes, cache associativity, number and type of functional units, etc., is inferred from the collected data.…”

Section: B Algorithm Complexitymentioning

confidence: 99%

Reducing the Cost of Measuring Memory Hierarchy Communication Parameters

Jiang

Sussman

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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For parallelizing compilers that target multi-core machines, some hardware information is very useful in producing optimized code. One approach to obtain such information is extracting the characteristics of the hardware from a set of performance data collected by performing extensive measurements on the computer system. However, such measurements tend to be heavy-weight and time-consuming, which makes them unable to complete in a reasonable amount of time, especially on a largescale system. We propose an algorithm to minimize the required measurements on a computer system using the tree structure of the memory hierarchy, that divides resources into equivalence classes so that different members of an equivalence class do not require separate measurements. Correctness arguments for the algorithms are presented, along with results that show the effectiveness and performance of the algorithms.

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Servet: A benchmark suite for autotuning on multicore clusters

Cited by 18 publications

References 18 publications

Efficient Characterization of Hidden Processor Memory Hierarchies

Efficient Characterization of Hidden Processor Memory Hierarchies

Memory aware load balance strategy on a parallel branch‐and‐bound application

Reducing the Cost of Measuring Memory Hierarchy Communication Parameters

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